From: Stefano Fedrigo Import in kernel 2.4.18-rmk4-mx1bsp tree the MX1BSP MMC external driver module. The original code is changed to: - Allow to mount MMC as root filesystem. - Detect and write SD cards. - Fix write to card (it worked only with 512 bytes blocks and data was not correctly written do card until release was called at umount). diff -Nru src.org/arch/arm/config.in src/arch/arm/config.in --- src.org/arch/arm/config.in Tue Oct 28 09:05:49 2003 +++ src/arch/arm/config.in Fri Sep 23 21:02:18 2005 @@ -510,6 +510,9 @@ source drivers/memdisk/Config.in source drivers/flashdisk/Config.in source drivers/sdramdisk/Config.in +if [ "$CONFIG_ARCH_MX1ADS" = "y" ]; then + source drivers/mx1mmc/Config.in +fi source drivers/pnp/Config.in source drivers/block/Config.in diff -Nru src.org/drivers/Makefile src/drivers/Makefile --- src.org/drivers/Makefile Tue Jul 22 15:41:10 2003 +++ src/drivers/Makefile Tue Sep 27 02:48:08 2005 @@ -8,7 +8,8 @@ mod-subdirs := dio mtd sbus video macintosh usb input telephony sgi ide \ message/i2o message/fusion scsi md ieee1394 pnp isdn atm \ - fc4 net/hamradio i2c l3 acpi bluetooth serial docbp memdisk flashdisk sdramdisk + fc4 net/hamradio i2c l3 acpi bluetooth serial \ + docbp memdisk flashdisk sdramdisk mx1mmc subdir-y := parport serial char block net sound misc media cdrom hotplug subdir-m := $(subdir-y) @@ -22,6 +23,7 @@ subdir-$(CONFIG_MEMDISK) += memdisk subdir-$(CONFIG_FLASHDISK) += flashdisk subdir-$(CONFIG_SDRAMDISK) += sdramdisk +subdir-$(CONFIG_MX1_MMC) += mx1mmc subdir-$(CONFIG_SBUS) += sbus subdir-$(CONFIG_ZORRO) += zorro subdir-$(CONFIG_NUBUS) += nubus diff -Nru src.org/drivers/mx1mmc/Config.in src/drivers/mx1mmc/Config.in --- src.org/drivers/mx1mmc/Config.in Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/Config.in Fri Sep 23 21:04:24 2005 @@ -0,0 +1,5 @@ +mainmenu_option next_comment +comment 'MX1 MMC driver' +tristate 'MX1 MMC driver' CONFIG_MX1_MMC +endmenu + diff -Nru src.org/drivers/mx1mmc/MX1_def.h src/drivers/mx1mmc/MX1_def.h --- src.org/drivers/mx1mmc/MX1_def.h Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/MX1_def.h Fri Sep 23 20:26:30 2005 @@ -0,0 +1,1245 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2002 Motorola Semiconductors HK Ltd + * + */ + +/****************************************************************************** + + C H E A D E R F I L E + + (c) Copyright Motorola Semiconductors Hong Kong Limited 2001-2002 + ALL RIGHTS RESERVED + +******************************************************************************* + + Project Name : DBMX1 System Test Program + Project No. : + Title : + Template Ver : 0.3 + File Name : MX1_def.h + Last Modified: Nov 14, 2001 + + Description : Definition header for DBMX1 silicon. + + Assumptions : NA + + Dependency Comments : NA + + Project Specific Data : NA + +******************************************************************************/ +#ifndef MX1_DEF_INC +#define MX1_DEF_INC + +#define DBMX1_BASE 0xF0000000 +/*************************** Header File Includes ****************************/ +/********************************* Constants *********************************/ +/******************************** Enumeration ********************************/ +/****************************** Basic Data types *****************************/ +/************************* Structure/Union Data types ************************/ +/********************************** Macros ***********************************/ + +/* common define for MX1 */ +//$0000 0000 - $000F FFFF Double Map Image 1 MB +//$0010 0000 - $001F FFFF Bootstrap ROM 1 MB +//$0020 0000 - $0020 0FFF AIPI1 4 KB +//$0020 1000 - $0020 1FFF WatchDog 4 KB +//$0020 2000 - $0020 2FFF TIMER1 4 KB +//$0020 3000 - $0020 3FFF TIMER2 4 KB +//$0020 4000 - $0020 4FFF RTC 4 KB +//$0020 5000 - $0020 5FFF LCD 4 KB +//$0020 6000 - $0020 6FFF UART1 4 KB +//$0020 7000 - $0020 7FFF UART2 4 KB +//$0020 8000 - $0020 8FFF PWM 4 KB +//$0020 9000 - $0020 9FFF DMA 4 KB +//$0020 A000 - $0020 AFFF Reserved 4 KB +//$0020 B000 - $0020 BFFF Reserved 4 KB +//$0020 C000 - $0020 CFFF Reserved 4 KB +//$0020 D000 - $0020 DFFF Reserved 4 KB +//$0020 E000 - $0020 EFFF Reserved 4 KB +//$0020 F000 - $0020 FFFF Reserved 4 KB +//$0021 0000 - $0021 0FFF AIPI2 4 KB +//$0021 1000 - $0021 1FFF SIM 4 KB +//$0021 2000 - $0021 2FFF USBD 4 KB +//$0021 3000 - $0021 3FFF CSPI 4 KB +//$0021 4000 - $0021 4FFF MMC 4 KB +//$0021 5000 - $0021 5FFF ASP 4 KB +//$0021 6000 - $0021 6FFF BTA 4 KB +//$0021 7000 - $0021 7FFF I2C 4 KB +//$0021 8000 - $0021 8FFF SSI 4 KB +//$0021 9000 - $0021 9FFF Reserved 4 KB +//$0021 A000 - $ 0021 AFFF Memory Stick 4 KB +//$0021 B000 - $0021 BFFF CRM 4 KB +//$0021 C000 - $ 0021 CFFF GPIO 4 KB +//$0021 D000 - $0021 DFFF Reserved 4 KB +//$0021 E000 - $0021 EFFF Reserved 4 KB +//$0021 F000 - $0021 FFFF Reserved 4 KB +//$0022 0000 - $0022 0FFF WEIM 4 KB +//$0022 1000 - $0022 1FFF SDRAMC 4 KB +//$0022 2000 - $0022 2FFF DSPA 4 KB +//$0022 3000 - $0022 3FFF AITC 4 KB +//$0022 4000 - $0022 4FFF CSI 4 KB +//$0022 5000 - $0022 5FFF Reserved 4 KB +//$0022 6000 - $0022 6FFF Reserved 4 KB +//$0022 7000 - $002F FFFF Reserved 868 KB + +// ; Memory Map +// ; ---------- +// ; $0020_0XXX aipi1 +// ; $0020_1XXX Watchdog (wdt_ip) +// ; $0020_2XXX Timer1 (timer_ip1) +// ; $0020_3XXX Timer2 (timer_ip2) +// ; $0020_4XXX RTC (rtc_ip) +// ; $0020_5XXX LCD (lcd_ip) +// ; $0020_6XXX UART1 (uart_ip1) +// ; $0020_7XXX UART2 (uart_ip2) +// ; $0020_8XXX PWM (pwm_ip) +// ; $0020_9XXX DMA (dma_ip) +// ; $0020_AXXX Reserved +// ; $0020_BXXX Reserved +// ; $0020_CXXX Reserved +// ; $0020_DXXX Reserved +// ; $0020_EXXX Reserved +// ; $0020_FXXX Reserved +// ; +// ; $0021_0XXX AIPI2 (dbmx_aipi2) +// ; $0021_1XXX SIM (sim_ip) +// ; $0021_2XXX USBD (usbd_ip) +// ; $0021_3XXX CSPI (cspi_ip) +// ; $0021_4XXX MMC (mmc_ip) +// ; $0021_5XXX ASP (asp_ip) +// ; $0021_6XXX BTA (bta_ip) +// ; $0021_7XXX I2C (i2c) +// ; $0021_8XXX SSI (ssi_ip) +// ; $0021_9XXX Video Port +// ; $0021_AXXX Memory Stick +// ; $0021_BXXX Clock & Reset (crm) +// ; $0021_CXXX GPIO (gpio_ip) +// ; $0021_DXXX Reserved +// ; $0021_EXXX Reserved +// ; $0021_FXXX Reserved +// ; +// ; $0022_0XXX Weim +// ; $0022_1XXX SDRAMC +// ; $0022_2XXX DSPA +// ; $0022_3XXX AITC +// ; $0022_4XXX Ext1 +// ; $0022_5XXX Ext2 +// ; $0022_6XXX Ext3 + +// ; ARM Program Status Register +// ; 31 30 29 28 27 7 6 5 4 +// ; ---------------------------------------------------------- +// ; | N | Z | C | V | Q | | I | F | T | | | | | | +// ; ---------------------------------------------------------- +// +// ;---------------------------------------; +// ;ARM modes ; +// ;---------------------------------------; +#define MODE_USR 0x10 +#define MODE_FIQ 0x11 +#define MODE_IRQ 0x12 +#define MODE_SVC 0x13 +#define MODE_ABT 0x17 +#define MODE_UND 0x1B +#define MODE_SYS 0x1F +#define MODE_BITS 0x1F +#define TBIT (1:SHL:5) +#define FBIT (1:SHL:6) +#define IBIT (1:SHL:7) +// +// ;---------------------------------------; +// ; ARM interrupts ; +// ;---------------------------------------; +#define INTERRUPT_BITS 0xC0 +#define ENABLE_IRQ 0x0 +#define ENABLE_FIQ 0x0 +#define DISABLE_FIQ 0x40 +#define DISABLE_IRQ 0x80 +// +// ;---------------------------------------; +// ; ARM FLAGS ; +// ;---------------------------------------; +#define FLAG_BITS 0xF0000000 +#define NFLAG 0x80000000 +#define ZFLAG 0x40000000 +#define CFLAG 0x20000000 +#define VFLAG 0x10000000 +// +// ;---------------------------------------; +// ; STACK ; +// ;---------------------------------------; +#define SVC_STACK TOP_OF_STACK // ; 003F_FDFF - 0040_0000 (512B) +#define IRQ_STACK (TOP_OF_STACK-0x200) // ; 003F_FBFF - 003F_FE00 (512B) +#define FIQ_STACK (TOP_OF_STACK-0x400) // ; 003F_F9FF - 003F_FC00 (512B) +#define USR_STACK (TOP_OF_STACK-0x600) // ; 003F_F7FF - 003F_FA00 (512B) +#define UND_STACK (TOP_OF_STACK-0x800) // ; 003F_F7FF - 003F_FA00 (512B) + +// ;---------------------------------------; +// ; AIPI1 ; +// ; $0020_0000 to $0020_0FFF ; +// ;---------------------------------------; +#define AIPI1_BASE_ADDR (DBMX1_BASE+0x00200000) // ; Peripheral Size Reg 0 +#define AIPI1_PSR0 AIPI1_BASE_ADDR // ; Peripheral Size Reg 1 +#define AIPI1_PSR1 (AIPI1_BASE_ADDR+0x04) +#define AIPI1_PAR (AIPI1_BASE_ADDR+0x08) // ; Peripheral Access Reg +// +// ;---------------------------------------; +// ; AIPI2 ; +// ; $0021_0000 to $0021_0FFF ; +// ;---------------------------------------; +#define AIPI2_BASE_ADDR (DBMX1_BASE+0x00210000) +#define AIPI2_PSR0 AIPI2_BASE_ADDR // ; Peripheral Size Reg 0 +#define AIPI2_PSR1 (AIPI2_BASE_ADDR+0x04) // ; Peripheral Size Reg 1 +#define AIPI2_PAR (AIPI2_BASE_ADDR+0x08) // ; Peripheral Access Reg +// +/* Register base address */ +#define PLL_BASE (DBMX1_BASE+0x0021B000) +// +/* Reset Module*/ +#define PLL_CSCR (PLL_BASE+0x00) //Clock Source Control Register +#define PLL_PCDR (PLL_BASE+0x20) //Peripherial Clock Divider Register +/* PLL & Clock Controller */ +#define PLL_MCTL0 (PLL_BASE+0x04) //MCU PLL Control Register 0 +#define PLL_MCTL1 (PLL_BASE+0x08) //MCU PLL Control Register 1 +#define PLL_UPCTL0 (PLL_BASE+0x0C) //USB PLL Control Register 0 +#define PLL_UPCTL1 (PLL_BASE+0x10) //USB PLL Control Register 1 +/* System Control */ +#define PLL_RSR (PLL_BASE+0x800) //Reset Source Register +#define PLL_SIDR (PLL_BASE+0x804) //Silicon ID Register +#define PLL_FMCR (PLL_BASE+0x808) //Function Muxing Control Register +#define PLL_GPCR (PLL_BASE+0x80C) //Global Peripherial Control Regiser +// ;---------------------------------------; +// ; AITC ; +// ; $0022_3000 to $0022_3FFF ; +// ;---------------------------------------; + +#define AITC_BASE_ADDR (DBMX1_BASE+0x00223000) +#define AITC_INTCNTL (AITC_BASE_ADDR+0x00) //Interrupt Control Register +#define AITC_NIMASK (AITC_BASE_ADDR+0x04) //Normal Interrupt Mask Register +#define AITC_INTENNUM (AITC_BASE_ADDR+0x08) //Interrupt Enable Number Register +#define AITC_INTDISNUM (AITC_BASE_ADDR+0x0C) //Interrupt Disable Number Register +#define AITC_INTENABLEH (AITC_BASE_ADDR+0x10) //Interrupt Enable Register High +#define AITC_INTENABLEL (AITC_BASE_ADDR+0x14) //Interrupt Enable Register Low +#define AITC_INTTYPEH (AITC_BASE_ADDR+0x18) +#define AITC_INTTYPEL (AITC_BASE_ADDR+0x1C) +#define AITC_NIPRIORITY7 (AITC_BASE_ADDR+0x20) +#define AITC_NIPRIORITY6 (AITC_BASE_ADDR+0x24) +#define AITC_NIPRIORITY5 (AITC_BASE_ADDR+0x28) +#define AITC_NIPRIORITY4 (AITC_BASE_ADDR+0x2C) +#define AITC_NIPRIORITY3 (AITC_BASE_ADDR+0x30) +#define AITC_NIPRIORITY2 (AITC_BASE_ADDR+0x34) +#define AITC_NIPRIORITY1 (AITC_BASE_ADDR+0x38) +#define AITC_NIPRIORITY0 (AITC_BASE_ADDR+0x3C) +#define AITC_NIVECSR (AITC_BASE_ADDR+0x40) +#define AITC_FIVECSR (AITC_BASE_ADDR+0x44) +#define AITC_INTSRCH (AITC_BASE_ADDR+0x48) +#define AITC_INTSRCL (AITC_BASE_ADDR+0x4C) +#define AITC_INTFRCH (AITC_BASE_ADDR+0x50) +#define AITC_INTFRCL (AITC_BASE_ADDR+0x54) +#define AITC_NIPNDH (AITC_BASE_ADDR+0x58) +#define AITC_NIPNDL (AITC_BASE_ADDR+0x5C) +#define AITC_FIPNDH (AITC_BASE_ADDR+0x60) +#define AITC_FIPNDL (AITC_BASE_ADDR+0x64) + + +#define INTCNTL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x00)) +#define NIMASK (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x04)) +#define INTENNUM (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x08)) +#define INTDISNUM (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x0C)) +#define INTENABLEH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x10)) +#define INTENABLEL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x14)) +#define INTTYPEH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x18)) +#define INTTYPEL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x1C)) +#define NIPRIORITY7 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x20)) +#define NIPRIORITY6 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x24)) +#define NIPRIORITY5 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x28)) +#define NIPRIORITY4 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x2C)) +#define NIPRIORITY3 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x30)) +#define NIPRIORITY2 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x34)) +#define NIPRIORITY1 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x38)) +#define NIPRIORITY0 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x3C)) +#define NIVECSR (*(volatile int *) (AITC_BASE_ADDR + 0x40)) +#define FIVECSR (*(volatile int *) (AITC_BASE_ADDR + 0x44)) +#define INTSRCH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x48)) +#define INTSRCL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x4C)) +#define INTFRCH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x50)) +#define INTFRCL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x54)) +#define NIPNDH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x58)) +#define NIPNDL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x5C)) +#define FIPNDH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x60)) +#define FIPNDL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x64)) + +// +// ;---------------------------------------; +// ; ASP ; +// ; $0021_5000 to $0021_5FFF ; +// ;---------------------------------------; +#define ASP_BASE_ADDR 0x00215000 +#define ASP_PADFIFO (ASP_BASE_ADDR+0x00) +#define ASP_VADFIFO (ASP_BASE_ADDR+0x04) +#define ASP_VDAFIFO (ASP_BASE_ADDR+0x08) +#define ASP_VADCOEF (ASP_BASE_ADDR+0x0C) +#define ASP_ACNTLCR (ASP_BASE_ADDR+0x10) +#define ASP_PSMPLRG (ASP_BASE_ADDR+0x14) +#define ASP_ICNTLR (ASP_BASE_ADDR+0x18) +#define ASP_ISTATR (ASP_BASE_ADDR+0x1C) +#define ASP_VADGAIN (ASP_BASE_ADDR+0x20) +#define ASP_VDAGAIN (ASP_BASE_ADDR+0x24) +#define ASP_VDACOEF (ASP_BASE_ADDR+0x28) +#define ASP_CLKDIV (ASP_BASE_ADDR+0x2C) +#define ASP_CMPCNTL (ASP_BASE_ADDR+0x30) +#define ASP_PTRREG (ASP_BASE_ADDR+0x34) +// +// ;---------------------------------------; +// ; BOOT ROM ; +// ;---------------------------------------; +#define BOOTROM_ADDR_BOT 0x00000000 +#define BOOTROM_PHY_SIZE 0x0000028C +#define BOOTROM_ASS_SIZE 0x00100000 +// +// ;---------------------------------------; +// ; BTA_WRAPPER ; +// ; $0021_6000 to $0021_6FFF ; +// ;---------------------------------------; +// ; Sequencer +#define BTA_BASE_ADDR 0x00216000 +#define BTA_COMMAND BTA_BASE_ADDR +#define BTA_STATUS BTA_BASE_ADDR +#define BTA_PACKETHEAD (BTA_BASE_ADDR+0x04) +#define BTA_PAYLOADHEAD (BTA_BASE_ADDR+0x08) +// +// ; BT clocks +#define BTA_NATIVECNT (BTA_BASE_ADDR+0x0C) +#define BTA_ESTCNT (BTA_BASE_ADDR+0x10) +#define BTA_OFFSETCNT (BTA_BASE_ADDR+0x14) +#define BTA_NATIVECLK_L (BTA_BASE_ADDR+0x18) +#define BTA_NATIVECLK_H (BTA_BASE_ADDR+0x1C) +#define BTA_ESTCLK_L (BTA_BASE_ADDR+0x20) +#define BTA_ESTCLK_H (BTA_BASE_ADDR+0x24) +#define BTA_OFFSETCLK_L (BTA_BASE_ADDR+0x28) +#define BTA_OFFSETCLK_H (BTA_BASE_ADDR+0x2C) +// +// ; BT pipeline +#define BTA_HECCRC (BTA_BASE_ADDR+0x30) +#define BTA_WHITE (BTA_BASE_ADDR+0x34) +#define BTA_ENCRYPT (BTA_BASE_ADDR+0x38) +// +// ; Radio Control +#define BTA_CORR_TIME (BTA_BASE_ADDR+0x40) +#define BTA_RF_GPO (BTA_BASE_ADDR+0x48) +#define BTA_RSSI (BTA_BASE_ADDR+0x4C) +#define BTA_TIME_AB (BTA_BASE_ADDR+0x50) +#define BTA_TIME_CD (BTA_BASE_ADDR+0x54) +#define BTA_PWM_TX (BTA_BASE_ADDR+0x58) +#define BTA_RF_CTRL (BTA_BASE_ADDR+0x5C) +#define BTA_RF_STATUS (BTA_BASE_ADDR+0x5C) +#define BTA_RX_TIME (BTA_BASE_ADDR+0x60) +#define BTA_TX_TIME (BTA_BASE_ADDR+0x64) +// ; Bit Reverse +#define BTA_WORD_REV (BTA_BASE_ADDR+0x178) +#define BTA_BYTE_REV (BTA_BASE_ADDR+0x17C) +// +// ; Timer +#define BTA_TIMER (BTA_BASE_ADDR+0x68) +// +// ; Correlator +#define BTA_THRESHOLD (BTA_BASE_ADDR+0x6C) +#define BTA_CORR_MAX (BTA_BASE_ADDR+0x6C) +#define BTA_SYNCHWORD_0 (BTA_BASE_ADDR+0x70) +#define BTA_SYNCHWORD_1 (BTA_BASE_ADDR+0x74) +#define BTA_SYNCHWORD_2 (BTA_BASE_ADDR+0x78) +#define BTA_SYNCHWORD_3 (BTA_BASE_ADDR+0x7C) +// +// ; BitBUF +#define BTA_BUF_WORD_0 (BTA_BASE_ADDR+0x80) +#define BTA_BUF_WORD_1 (BTA_BASE_ADDR+0x84) +#define BTA_BUF_WORD_2 (BTA_BASE_ADDR+0x88) +#define BTA_BUF_WORD_3 (BTA_BASE_ADDR+0x8C) +#define BTA_BUF_WORD_4 (BTA_BASE_ADDR+0x90) +#define BTA_BUF_WORD_5 (BTA_BASE_ADDR+0x94) +#define BTA_BUF_WORD_6 (BTA_BASE_ADDR+0x98) +#define BTA_BUF_WORD_7 (BTA_BASE_ADDR+0x9C) +#define BTA_BUF_WORD_8 (BTA_BASE_ADDR+0xA0) +#define BTA_BUF_WORD_9 (BTA_BASE_ADDR+0xA4) +#define BTA_BUF_WORD_10 (BTA_BASE_ADDR+0xA8) +#define BTA_BUF_WORD_11 (BTA_BASE_ADDR+0xAC) +#define BTA_BUF_WORD_12 (BTA_BASE_ADDR+0xB0) +#define BTA_BUF_WORD_13 (BTA_BASE_ADDR+0xB4) +#define BTA_BUF_WORD_14 (BTA_BASE_ADDR+0xB8) +#define BTA_BUF_WORD_15 (BTA_BASE_ADDR+0xBC) +#define BTA_BUF_WORD_16 (BTA_BASE_ADDR+0xC0) +#define BTA_BUF_WORD_17 (BTA_BASE_ADDR+0xC4) +#define BTA_BUF_WORD_18 (BTA_BASE_ADDR+0xC8) +#define BTA_BUF_WORD_19 (BTA_BASE_ADDR+0xCC) +#define BTA_BUF_WORD_20 (BTA_BASE_ADDR+0xD0) +#define BTA_BUF_WORD_21 (BTA_BASE_ADDR+0xD4) +#define BTA_BUF_WORD_22 (BTA_BASE_ADDR+0xD8) +#define BTA_BUF_WORD_23 (BTA_BASE_ADDR+0xDC) +#define BTA_BUF_WORD_24 (BTA_BASE_ADDR+0xE0) +#define BTA_BUF_WORD_25 (BTA_BASE_ADDR+0xE4) +#define BTA_BUF_WORD_26 (BTA_BASE_ADDR+0xE8) +#define BTA_BUF_WORD_27 (BTA_BASE_ADDR+0xEC) +#define BTA_BUF_WORD_28 (BTA_BASE_ADDR+0xF0) +#define BTA_BUF_WORD_29 (BTA_BASE_ADDR+0xF4) +#define BTA_BUF_WORD_30 (BTA_BASE_ADDR+0xF8) +#define BTA_BUF_WORD_31 (BTA_BASE_ADDR+0xFC) +// +// ; Wakeup +#define BTA_WU_1 (BTA_BASE_ADDR+0x100) +#define BTA_WU_2 (BTA_BASE_ADDR+0x104) +#define BTA_WU_3 (BTA_BASE_ADDR+0x108) +#define BTA_WU_DELTA3 (BTA_BASE_ADDR+0x108) +#define BTA_WU_4 (BTA_BASE_ADDR+0x10C) +#define BTA_WU_DELTA4 (BTA_BASE_ADDR+0x10C) +#define BTA_WU_CTRL (BTA_BASE_ADDR+0x110) +#define BTA_WU_STATUS (BTA_BASE_ADDR+0x110) +#define BTA_WU_COUNT (BTA_BASE_ADDR+0x114) +// +// ; Clock control +#define BTA_CLK_CTRL (BTA_BASE_ADDR+0x118) +// +// ; SPI +#define BTA_SPI_WORD_0 (BTA_BASE_ADDR+0x120) +#define BTA_SPI_WORD_1 (BTA_BASE_ADDR+0x124) +#define BTA_SPI_WORD_2 (BTA_BASE_ADDR+0x128) +#define BTA_SPI_WORD_3 (BTA_BASE_ADDR+0x12C) +#define BTA_SPI_WADDR (BTA_BASE_ADDR+0x130) +#define BTA_SPI_RADDR (BTA_BASE_ADDR+0x134) +#define BTA_SPI_CTRL (BTA_BASE_ADDR+0x138) +#define BTA_SPI_STATUS (BTA_BASE_ADDR+0x138) +// +// ; Frequency Hopping +#define BTA_HOPWORDS_0 (BTA_BASE_ADDR+0x140) +#define BTA_FREQ_OUT (BTA_BASE_ADDR+0x140) +#define BTA_HOPWORDS_1 (BTA_BASE_ADDR+0x144) +#define BTA_HOPWORDS_2 (BTA_BASE_ADDR+0x148) +#define BTA_HOPWORDS_3 (BTA_BASE_ADDR+0x14C) +#define BTA_HOPWORDS_4 (BTA_BASE_ADDR+0x150) +// +// ; Interrupt +#define BTA_INTERRUPT (BTA_BASE_ADDR+0x160) +// +// ; MLSE +#define BTA_SYNC_METRIC (BTA_BASE_ADDR+0x170) +#define BTA_SYNC_FC (BTA_BASE_ADDR+0x174) +// +// ;---------------------------------------; +// ; Clock & Reset (CRM) ; +// ; $0021_B000 to $0021_BFFF ; +// ;---------------------------------------; +#define CRM_BASE_ADDR (DBMX1_BASE+0x0021B000) +#define CRM_CSCR CRM_BASE_ADDR // ; Clock Source Control Reg +#define CRM_MPCTL0 (CRM_BASE_ADDR+0x04) // ; MCU PLL Control Reg +#define CRM_MPCTL1 (CRM_BASE_ADDR+0x08) // ; MCU PLL & System Clk Ctl Reg +#define CRM_UPCTL0 (CRM_BASE_ADDR+0x0C) // ; USB PLL Control Reg 0 +#define CRM_UPCTL1 (CRM_BASE_ADDR+0x10) // ; USB PLL Control Reg 1 +#define CRM_PCDR (CRM_BASE_ADDR+0x20) // ; Perpheral Clock Divider Reg +// +#define CRM_RSR (CRM_BASE_ADDR+0x800) // ; Reset Source Reg +#define CRM_SIDR (CRM_BASE_ADDR+0x804) // ; Silicon ID Reg +#define CRM_FMCR (CRM_BASE_ADDR+0x808) // ; Functional Muxing Control Reg +#define CRM_GPCR (CRM_BASE_ADDR+0x80C) // ; Global Control Reg +// ;---------------------------------------; +// ; CSI +// ; $0022_4000 to $0022_4FFF ; +// ;---------------------------------------; +#define CSI_BASE_ADDR 0x00224000 +#define CSI_CTRL_REG1 (CSI_BASE_ADDR+0x00) +#define CSI_CTRL_REG2 (CSI_BASE_ADDR+0x04) +#define CSI_STS_REG (CSI_BASE_ADDR+0x08) +#define CSI_STAT_FIFO (CSI_BASE_ADDR+0x0C) +#define CSI_RX_FIFO (CSI_BASE_ADDR+0x10) +// +// ;---------------------------------------; +// ; CSPI ; +// ; $0021_3000 to $0021_3FFF ; +// ;---------------------------------------; +#define CSPI_BASE_ADDR 0x00213000 +#define CSPI_SPIRXD CSPI_BASE_ADDR +#define CSPI_SPITXD (CSPI_BASE_ADDR+0x04) +#define CSPI_SPICONT1 (CSPI_BASE_ADDR+0x08) +#define CSPI_INTCS (CSPI_BASE_ADDR+0x0C) +#define CSPI_SPITEST (CSPI_BASE_ADDR+0x10) +#define CSPI_SPISPCR (CSPI_BASE_ADDR+0x14) +#define CSPI_SPIDMA (CSPI_BASE_ADDR+0x18) +#define CSPI_SPIRESET (CSPI_BASE_ADDR+0x1C) +// +// ;---------------------------------------; +// ; DMA ; +// ; $0020_9000 to $0020_9FFF ; +// ;---------------------------------------; +#define DMA_BASE_ADDR 0x00209000 +#define DMA_SYS_BASE (DMA_BASE_ADDR+0x000) +#define DMA_M2D_BASE (DMA_BASE_ADDR+0x040) +#define DMA_CH0_BASE (DMA_BASE_ADDR+0x080) +#define DMA_CH1_BASE (DMA_BASE_ADDR+0x0C0) +#define DMA_CH2_BASE (DMA_BASE_ADDR+0x100) +#define DMA_CH3_BASE (DMA_BASE_ADDR+0x140) +#define DMA_CH4_BASE (DMA_BASE_ADDR+0x180) +#define DMA_CH5_BASE (DMA_BASE_ADDR+0x1C0) +#define DMA_CH6_BASE (DMA_BASE_ADDR+0x200) +#define DMA_CH7_BASE (DMA_BASE_ADDR+0x240) +#define DMA_CH8_BASE (DMA_BASE_ADDR+0x280) +#define DMA_CH9_BASE (DMA_BASE_ADDR+0x2C0) +#define DMA_CH10_BASE (DMA_BASE_ADDR+0x300) +#define DMA_TST_BASE (DMA_BASE_ADDR+0x340) +// +#define DMA_DCR (DMA_SYS_BASE+0x000) +#define DMA_ISR (DMA_SYS_BASE+0x004) +#define DMA_IMR (DMA_SYS_BASE+0x008) +#define DMA_BTOSR (DMA_SYS_BASE+0x00C) +#define DMA_RTOSR (DMA_SYS_BASE+0x010) +#define DMA_TESR (DMA_SYS_BASE+0x014) +#define DMA_BOSR (DMA_SYS_BASE+0x018) +#define DMA_BTOCR (DMA_SYS_BASE+0x01C) +// +#define DMA_WSRA (DMA_M2D_BASE+0x000) +#define DMA_XSRA (DMA_M2D_BASE+0x004) +#define DMA_YSRA (DMA_M2D_BASE+0x008) +#define DMA_WSRB (DMA_M2D_BASE+0x00C) +#define DMA_XSRB (DMA_M2D_BASE+0x010) +#define DMA_YSRB (DMA_M2D_BASE+0x014) +// +#define DMA_SAR0 (DMA_CH0_BASE+0x000) +#define DMA_DAR0 (DMA_CH0_BASE+0x004) +#define DMA_CNTR0 (DMA_CH0_BASE+0x008) +#define DMA_CCR0 (DMA_CH0_BASE+0x00C) +#define DMA_RSSR0 (DMA_CH0_BASE+0x010) +#define DMA_BLR0 (DMA_CH0_BASE+0x014) +#define DMA_RTOR0 (DMA_CH0_BASE+0x018) +#define DMA_BUCR0 (DMA_CH0_BASE+0x018) +// +#define DMA_SAR1 (DMA_CH1_BASE+0x000) +#define DMA_DAR1 (DMA_CH1_BASE+0x004) +#define DMA_CNTR1 (DMA_CH1_BASE+0x008) +#define DMA_CCR1 (DMA_CH1_BASE+0x00C) +#define DMA_RSSR1 (DMA_CH1_BASE+0x010) +#define DMA_BLR1 (DMA_CH1_BASE+0x014) +#define DMA_RTOR1 (DMA_CH1_BASE+0x018) +#define DMA_BUCR1 (DMA_CH1_BASE+0x018) +// +#define DMA_SAR2 (DMA_CH2_BASE+0x000) +#define DMA_DAR2 (DMA_CH2_BASE+0x004) +#define DMA_CNTR2 (DMA_CH2_BASE+0x008) +#define DMA_CCR2 (DMA_CH2_BASE+0x00C) +#define DMA_RSSR2 (DMA_CH2_BASE+0x010) +#define DMA_BLR2 (DMA_CH2_BASE+0x014) +#define DMA_RTOR2 (DMA_CH2_BASE+0x018) +#define DMA_BUCR2 (DMA_CH2_BASE+0x018) +// +#define DMA_SAR3 (DMA_CH3_BASE+0x000) +#define DMA_DAR3 (DMA_CH3_BASE+0x004) +#define DMA_CNTR3 (DMA_CH3_BASE+0x008) +#define DMA_CCR3 (DMA_CH3_BASE+0x00C) +#define DMA_RSSR3 (DMA_CH3_BASE+0x010) +#define DMA_BLR3 (DMA_CH3_BASE+0x014) +#define DMA_RTOR3 (DMA_CH3_BASE+0x018) +#define DMA_BUCR3 (DMA_CH3_BASE+0x018) +// +#define DMA_SAR4 (DMA_CH4_BASE+0x000) +#define DMA_DAR4 (DMA_CH4_BASE+0x004) +#define DMA_CNTR4 (DMA_CH4_BASE+0x008) +#define DMA_CCR4 (DMA_CH4_BASE+0x00C) +#define DMA_RSSR4 (DMA_CH4_BASE+0x010) +#define DMA_BLR4 (DMA_CH4_BASE+0x014) +#define DMA_RTOR4 (DMA_CH4_BASE+0x018) +#define DMA_BUCR4 (DMA_CH4_BASE+0x018) +// +#define DMA_SAR5 (DMA_CH5_BASE+0x000) +#define DMA_DAR5 (DMA_CH5_BASE+0x004) +#define DMA_CNTR5 (DMA_CH5_BASE+0x008) +#define DMA_CCR5 (DMA_CH5_BASE+0x00C) +#define DMA_RSSR5 (DMA_CH5_BASE+0x010) +#define DMA_BLR5 (DMA_CH5_BASE+0x014) +#define DMA_RTOR5 (DMA_CH5_BASE+0x018) +#define DMA_BUCR5 (DMA_CH5_BASE+0x018) +// +#define DMA_SAR6 (DMA_CH6_BASE+0x000) +#define DMA_DAR6 (DMA_CH6_BASE+0x004) +#define DMA_CNTR6 (DMA_CH6_BASE+0x008) +#define DMA_CCR6 (DMA_CH6_BASE+0x00C) +#define DMA_RSSR6 (DMA_CH6_BASE+0x010) +#define DMA_BLR6 (DMA_CH6_BASE+0x014) +#define DMA_RTOR6 (DMA_CH6_BASE+0x018) +#define DMA_BUCR6 (DMA_CH6_BASE+0x018) +// +#define DMA_SAR7 (DMA_CH7_BASE+0x000) +#define DMA_DAR7 (DMA_CH7_BASE+0x004) +#define DMA_CNTR7 (DMA_CH7_BASE+0x008) +#define DMA_CCR7 (DMA_CH7_BASE+0x00C) +#define DMA_RSSR7 (DMA_CH7_BASE+0x010) +#define DMA_BLR7 (DMA_CH7_BASE+0x014) +#define DMA_RTOR7 (DMA_CH7_BASE+0x018) +#define DMA_BUCR7 (DMA_CH7_BASE+0x018) +// +#define DMA_SAR8 (DMA_CH8_BASE+0x000) +#define DMA_DAR8 (DMA_CH8_BASE+0x004) +#define DMA_CNTR8 (DMA_CH8_BASE+0x008) +#define DMA_CCR8 (DMA_CH8_BASE+0x00C) +#define DMA_RSSR8 (DMA_CH8_BASE+0x010) +#define DMA_BLR8 (DMA_CH8_BASE+0x014) +#define DMA_RTOR8 (DMA_CH8_BASE+0x018) +#define DMA_BUCR8 (DMA_CH8_BASE+0x018) +// +#define DMA_SAR9 (DMA_CH9_BASE+0x000) +#define DMA_DAR9 (DMA_CH9_BASE+0x004) +#define DMA_CNTR9 (DMA_CH9_BASE+0x008) +#define DMA_CCR9 (DMA_CH9_BASE+0x00C) +#define DMA_RSSR9 (DMA_CH9_BASE+0x010) +#define DMA_BLR9 (DMA_CH9_BASE+0x014) +#define DMA_RTOR9 (DMA_CH9_BASE+0x018) +#define DMA_BUCR9 (DMA_CH9_BASE+0x018) +// +#define DMA_SAR10 (DMA_CH10_BASE+0x000) +#define DMA_DAR10 (DMA_CH10_BASE+0x004) +#define DMA_CNTR10 (DMA_CH10_BASE+0x008) +#define DMA_CCR10 (DMA_CH10_BASE+0x00C) +#define DMA_RSSR10 (DMA_CH10_BASE+0x010) +#define DMA_BLR10 (DMA_CH10_BASE+0x014) +#define DMA_RTOR10 (DMA_CH10_BASE+0x018) +#define DMA_BUCR10 (DMA_CH10_BASE+0x018) +// +#define DMA_TCR (DMA_TST_BASE+0x000) +#define DMA_TFIFOA (DMA_TST_BASE+0x004) +#define DMA_TDRR (DMA_TST_BASE+0x008) +#define DMA_TDIPR (DMA_TST_BASE+0x00C) +#define DMA_TFIFOB (DMA_TST_BASE+0x010) +// +// ;---------------------------------------; +// ; DSPA ; +// ; $0022_2000 to $0022_2FFF ; +// ;---------------------------------------; +#define DSPA_BASE_ADDR 0x00222000 +// +#define DSPA_MAC_MOD (DSPA_BASE_ADDR+0x0000) +#define DSPA_MAC_CTRL (DSPA_BASE_ADDR+0x0004) +#define DSPA_MAC_MULT (DSPA_BASE_ADDR+0x0008) +#define DSPA_MAC_ACCU (DSPA_BASE_ADDR+0x000C) +#define DSPA_MAC_INTR (DSPA_BASE_ADDR+0x0010) +#define DSPA_MAC_INTR_MASK (DSPA_BASE_ADDR+0x0014) +#define DSPA_MAC_FIFO (DSPA_BASE_ADDR+0x0018) +#define DSPA_MAC_FIFO_STAT (DSPA_BASE_ADDR+0x001C) +#define DSPA_MAC_BURST (DSPA_BASE_ADDR+0x0020) +#define DSPA_MAC_BIT_SEL (DSPA_BASE_ADDR+0x0024) +// +#define DSPA_MAC_XBASE (DSPA_BASE_ADDR+0x0200) +#define DSPA_MAC_XINDEX (DSPA_BASE_ADDR+0x0204) +#define DSPA_MAC_XLENGTH (DSPA_BASE_ADDR+0x0208) +#define DSPA_MAC_XMODIFY (DSPA_BASE_ADDR+0x020C) +#define DSPA_MAC_XINCR (DSPA_BASE_ADDR+0x0210) +#define DSPA_MAC_XCOUNT (DSPA_BASE_ADDR+0x0214) +// +#define DSPA_MAC_YBASE (DSPA_BASE_ADDR+0x0300) +#define DSPA_MAC_YINDEX (DSPA_BASE_ADDR+0x0304) +#define DSPA_MAC_YLENGTH (DSPA_BASE_ADDR+0x0308) +#define DSPA_MAC_YMODIFY (DSPA_BASE_ADDR+0x030C) +#define DSPA_MAC_YINCR (DSPA_BASE_ADDR+0x0310) +#define DSPA_MAC_YCOUNT (DSPA_BASE_ADDR+0x0314) +// +#define DSPA_DCTCTRL (DSPA_BASE_ADDR+0x0400) +#define DSPA_DCTVER (DSPA_BASE_ADDR+0x0404) +#define DSPA_DCTIRQENA (DSPA_BASE_ADDR+0x0408) +#define DSPA_DCTIRQSTAT (DSPA_BASE_ADDR+0x040C) +#define DSPA_DCTSRCADD (DSPA_BASE_ADDR+0x0410) +#define DSPA_DCTDESADD (DSPA_BASE_ADDR+0x0414) +#define DSPA_DCTFIFO (DSPA_BASE_ADDR+0x0500) +// +// ;---------------------------------------; +// ; ESRAM ; +// ; $0030_D000 to $0031_FFFF ; +// ;---------------------------------------; +#define eSRAM_ADDR_BOT 0x00300000 // ; Bottom of eSRAM +#define eSRAM_ADDR_TOP 0x00319000 // ; Top of physical eSRAM +#define eSRAM_ADDR_LMT 0x003FFFFF // ; Limit of allocated eSRAM +#define eSRAM_PHY_SIZE 0x00018000 // ; Physical size of eSRAM (96k) +#define eSRAM_ASS_SIZE 0x00100000 // ; Assigned size of eSRAM (1M) +#define eSRAM_8K_SIZE 0x00008000 // ; 8k byte size for boundary between RAM1 & RAM2 +// +// ;---------------------------------------; +// ; GPIO - PTA ; +// ; $0021_C000 to $0021_C0FF ; +// ;---------------------------------------; +#define PTA_BASE_ADDR (DBMX1_BASE + 0x0021C000) +#define PTA_DDIR PTA_BASE_ADDR +#define PTA_OCR1 (PTA_BASE_ADDR+0x04) +#define PTA_OCR2 (PTA_BASE_ADDR+0x08) +#define PTA_ICONFA1 (PTA_BASE_ADDR+0x0C) +#define PTA_ICONFA2 (PTA_BASE_ADDR+0x10) +#define PTA_ICONFB1 (PTA_BASE_ADDR+0x14) +#define PTA_ICONFB2 (PTA_BASE_ADDR+0x18) +#define PTA_DR (PTA_BASE_ADDR+0x1C) +#define PTA_GIUS (PTA_BASE_ADDR+0x20) +#define PTA_SSR (PTA_BASE_ADDR+0x24) +#define PTA_ICR1 (PTA_BASE_ADDR+0x28) +#define PTA_ICR2 (PTA_BASE_ADDR+0x2C) +#define PTA_IMR (PTA_BASE_ADDR+0x30) +#define PTA_ISR (PTA_BASE_ADDR+0x34) +#define PTA_GPR (PTA_BASE_ADDR+0x38) +#define PTA_SWR (PTA_BASE_ADDR+0x3C) +#define PTA_PUEN (PTA_BASE_ADDR+0x40) +// +// ;---------------------------------------; +// ; GPIO - PTB ; +// ; $0021_C100 to $0021_C1FF ; +// ;---------------------------------------; +#define PTB_BASE_ADDR (DBMX1_BASE + 0x0021C100) +#define PTB_DDIR PTB_BASE_ADDR +#define PTB_OCR1 (PTB_BASE_ADDR+0x04) +#define PTB_OCR2 (PTB_BASE_ADDR+0x08) +#define PTB_ICONFA1 (PTB_BASE_ADDR+0x0C) +#define PTB_ICONFA2 (PTB_BASE_ADDR+0x10) +#define PTB_ICONFB1 (PTB_BASE_ADDR+0x14) +#define PTB_ICONFB2 (PTB_BASE_ADDR+0x18) +#define PTB_DR (PTB_BASE_ADDR+0x1C) +#define PTB_GIUS (PTB_BASE_ADDR+0x20) +#define PTB_SSR (PTB_BASE_ADDR+0x24) +#define PTB_ICR1 (PTB_BASE_ADDR+0x28) +#define PTB_ICR2 (PTB_BASE_ADDR+0x2C) +#define PTB_IMR (PTB_BASE_ADDR+0x30) +#define PTB_ISR (PTB_BASE_ADDR+0x34) +#define PTB_GPR (PTB_BASE_ADDR+0x38) +#define PTB_SWR (PTB_BASE_ADDR+0x3C) +#define PTB_PUEN (PTB_BASE_ADDR+0x40) + +// ;---------------------------------------; +// ; GPIO - PTC ; +// ; $0021_C200 to $0021_C2FF ; +// ;---------------------------------------; +#define PTC_BASE_ADDR (DBMX1_BASE+0x0021C200) +#define PTC_DDIR PTC_BASE_ADDR +#define PTC_OCR1 (PTC_BASE_ADDR+0x04) +#define PTC_OCR2 (PTC_BASE_ADDR+0x08) +#define PTC_ICONFA1 (PTC_BASE_ADDR+0x0C) +#define PTC_ICONFA2 (PTC_BASE_ADDR+0x10) +#define PTC_ICONFB1 (PTC_BASE_ADDR+0x14) +#define PTC_ICONFB2 (PTC_BASE_ADDR+0x18) +#define PTC_DR (PTC_BASE_ADDR+0x1C) +#define PTC_GIUS (PTC_BASE_ADDR+0x20) +#define PTC_SSR (PTC_BASE_ADDR+0x24) +#define PTC_ICR1 (PTC_BASE_ADDR+0x28) +#define PTC_ICR2 (PTC_BASE_ADDR+0x2C) +#define PTC_IMR (PTC_BASE_ADDR+0x30) +#define PTC_ISR (PTC_BASE_ADDR+0x34) +#define PTC_GPR (PTC_BASE_ADDR+0x38) +#define PTC_SWR (PTC_BASE_ADDR+0x3C) +#define PTC_PUEN (PTC_BASE_ADDR+0x40) + +// ;---------------------------------------; +// ; GPIO - PTD ; +// ; $0021_C300 to $0021_C3FF ; +// ;---------------------------------------; +#define PTD_BASE_ADDR (DBMX1_BASE+0x0021C300) +#define PTD_DDIR PTD_BASE_ADDR +#define PTD_OCR1 (PTD_BASE_ADDR+0x04) +#define PTD_OCR2 (PTD_BASE_ADDR+0x08) +#define PTD_ICONFA1 (PTD_BASE_ADDR+0x0C) +#define PTD_ICONFA2 (PTD_BASE_ADDR+0x10) +#define PTD_ICONFB1 (PTD_BASE_ADDR+0x14) +#define PTD_ICONFB2 (PTD_BASE_ADDR+0x18) +#define PTD_DR (PTD_BASE_ADDR+0x1C) +#define PTD_GIUS (PTD_BASE_ADDR+0x20) +#define PTD_SSR (PTD_BASE_ADDR+0x24) +#define PTD_ICR1 (PTD_BASE_ADDR+0x28) +#define PTD_ICR2 (PTD_BASE_ADDR+0x2C) +#define PTD_IMR (PTD_BASE_ADDR+0x30) +#define PTD_ISR (PTD_BASE_ADDR+0x34) +#define PTD_GPR (PTD_BASE_ADDR+0x38) +#define PTD_SWR (PTD_BASE_ADDR+0x3C) +#define PTD_PUEN (PTD_BASE_ADDR+0x40) +// +// ;---------------------------------------; +// ; LCDC ; +// ; $0020_5000 to $0020_5FFF ; +// ;---------------------------------------; +#define LCDC_BASE_ADDR 0x00205000 +#define LCDC_PAL_ADDR 0x00205800 +#define LCDC_ssa LCDC_BASE_ADDR +#define LCDC_xymax (LCDC_BASE_ADDR+0x04) +#define LCDC_vpw (LCDC_BASE_ADDR+0x08) +#define LCDC_hcc_xy (LCDC_BASE_ADDR+0x0C) +#define LCDC_hcc_w (LCDC_BASE_ADDR+0x10) +#define LCDC_chcc (LCDC_BASE_ADDR+0x14) +#define LCDC_con (LCDC_BASE_ADDR+0x18) +#define LCDC_hsyn (LCDC_BASE_ADDR+0x1C) +#define LCDC_vsyn (LCDC_BASE_ADDR+0x20) +#define LCDC_pan (LCDC_BASE_ADDR+0x24) +#define LCDC_gpm (LCDC_BASE_ADDR+0x28) +#define LCDC_pwm (LCDC_BASE_ADDR+0x2C) +#define LCDC_dma (LCDC_BASE_ADDR+0x30) +#define LCDC_self (LCDC_BASE_ADDR+0x34) +#define LCDC_int (LCDC_BASE_ADDR+0x38) +#define LCDC_status (LCDC_BASE_ADDR+0x40) +#define LCDC_ram_0 LCDC_PAL_ADDR +#define LCDC_ram_1 (LCDC_PAL_ADDR+0x04) +#define LCDC_ram_2 (LCDC_PAL_ADDR+0x08) +#define LCDC_ram_3 (LCDC_PAL_ADDR+0x0C) +#define LCDC_ram_4 (LCDC_PAL_ADDR+0x10) +#define LCDC_ram_5 (LCDC_PAL_ADDR+0x14) +#define LCDC_ram_6 (LCDC_PAL_ADDR+0x18) +#define LCDC_ram_7 (LCDC_PAL_ADDR+0x1C) +#define LCDC_ram_8 (LCDC_PAL_ADDR+0x20) +#define LCDC_ram_9 (LCDC_PAL_ADDR+0x24) +#define LCDC_ram_a (LCDC_PAL_ADDR+0x28) +#define LCDC_ram_b (LCDC_PAL_ADDR+0x2C) +#define LCDC_ram_c (LCDC_PAL_ADDR+0x30) +#define LCDC_ram_d (LCDC_PAL_ADDR+0x34) +#define LCDC_ram_e (LCDC_PAL_ADDR+0x38) +#define LCDC_ram_f (LCDC_PAL_ADDR+0x3c) +// +// ;---------------------------------------; +// ; I2C ; +// ; $0021_7000 to $0021_7FFF ; +// ;---------------------------------------; +// +#define I2C_BASE_ADDR 0x00217000 +#define I2C_IADR I2C_BASE_ADDR +#define I2C_IFDR (I2C_BASE_ADDR+0x04) +#define I2C_I2CR (I2C_BASE_ADDR+0x08) +#define I2C_I2SR (I2C_BASE_ADDR+0x0C) +#define I2C_I2DR (I2C_BASE_ADDR+0x10) +// +// ;---------------------------------------; +// ; SSI ; +// ; $0021_8000 to $0021_8FFF ; +// ;---------------------------------------; +#define SSI_BASE_ADDR 0x00218000 +#define SSI_STX SSI_BASE_ADDR +#define SSI_SRX (SSI_BASE_ADDR+0x04) +#define SSI_SCSR (SSI_BASE_ADDR+0x08) +#define SSI_STCR (SSI_BASE_ADDR+0x0C) +#define SSI_SRCR (SSI_BASE_ADDR+0x10) +#define SSI_STCCR (SSI_BASE_ADDR+0x14) +#define SSI_SRCCR (SSI_BASE_ADDR+0x18) +#define SSI_STSR (SSI_BASE_ADDR+0x1C) +#define SSI_SFCSR (SSI_BASE_ADDR+0x20) +#define SSI_STR (SSI_BASE_ADDR+0x24) +#define SSI_SOR (SSI_BASE_ADDR+0x28) +// +// ;---------------------------------------; +// ; MMC all the address used for SDHC ; +// ; $0021_4000 to $0021_4FFF ; +// ;---------------------------------------; +// +#define MMC_BASE_ADDR 0x00214000 +#define MMC_STR_STP_CLK MMC_BASE_ADDR +#define MMC_STATUS (MMC_BASE_ADDR+0x04) +#define MMC_CLK_RATE (MMC_BASE_ADDR+0x08) +#define MMC_CMD_DAT_CONT (MMC_BASE_ADDR+0x0C) +#define MMC_RESPONSE_TO (MMC_BASE_ADDR+0x10) +#define MMC_READ_TO (MMC_BASE_ADDR+0x14) +#define MMC_BLK_LEN (MMC_BASE_ADDR+0x18) +#define MMC_NOB (MMC_BASE_ADDR+0x1C) +#define MMC_REV_NO (MMC_BASE_ADDR+0x20) +#define MMC_INT_MASK (MMC_BASE_ADDR+0x24) +#define MMC_CMD (MMC_BASE_ADDR+0x28) +#define MMC_ARGH (MMC_BASE_ADDR+0x2C) +#define MMC_ARGL (MMC_BASE_ADDR+0x30) +#define MMC_RES_FIFO (MMC_BASE_ADDR+0x34) +#define MMC_BUFFER_ACCESS (MMC_BASE_ADDR+0x38) +#define MMC_BUF_PART_FULL (MMC_BASE_ADDR+0x3C) +#define MMC_OTHERS_REGS_1 (MMC_BASE_ADDR+0x40) +#define MMC_OTHERS_REGS_2 (MMC_BASE_ADDR+0x80) +#define MMC_OTHERS_REGS_3 (MMC_BASE_ADDR+0x100) +#define MMC_OTHERS_REGS_4 (MMC_BASE_ADDR+0x200) +#define MMC_OTHERS_REGS_5 (MMC_BASE_ADDR+0x400) +#define MMC_OTHERS_REGS_6 (MMC_BASE_ADDR+0x800) +// +// ;---------------------------------------; +// ; MSHC ; +// ; $0021_A000 to $0021_AFFF ; +// ;---------------------------------------; +#define MSHC_BASE_ADDR 0x0021A000 +#define MSHC_MSCMD (U16 *)MSHC_BASE_ADDR // ; Command Reg +#define MSHC_MSCS (U16 *)(MSHC_BASE_ADDR+0x02) // ; Control/Status Reg +#define MSHC_MSDATA (U16 *)(MSHC_BASE_ADDR+0x04) // ; Tx/Rx FIFO Reg +#define MSHC_MSICS (U16 *)(MSHC_BASE_ADDR+0x06) // ; Interrupt Control/Status Reg +#define MSHC_MSPPCD (U16 *)(MSHC_BASE_ADDR+0x08) // ; Parallel Port Control/Data Reg +#define MSHC_MSC2 (U16 *)(MSHC_BASE_ADDR+0x0A) // ; Control2 Reg +#define MSHC_MSACMD (U16 *)(MSHC_BASE_ADDR+0x0C) // ; Auto Command Reg +#define MSHC_MSFAECS (U16 *)(MSHC_BASE_ADDR+0x0E) // ; FIFO Acc Err Ctrl/Status Reg +#define MSHC_MSCLKD (U16 *)(MSHC_BASE_ADDR+0x10) // ; Serial Clock Div Control Reg +#define MSHC_MSDRQC (U16 *)(MSHC_BASE_ADDR+0x12) // ; DMA Request Control Reg +// +// ;---------------------------------------; +// ; PORTHOLE ; +// ;---------------------------------------; +#define EVENT_PORTHOLE 0x12301000 // ; User Event Porthole +#define EVENT_PH 0x12301000 +#define EVENT 0x12301000 +#define PASS_PORTHOLE 0x12301004 +#define PASS_PH 0x12301004 +#define FAIL_PORTHOLE 0x12301008 +#define FAIL_PH 0x12301008 +#define STOP_PORTHOLE 0x1230100C +#define STOP_PH 0x1230100C +#define FINISH_PORTHOLE 0x12301010 +#define FINISH_PH 0x12301010 +// +#define EXP_DATA_PH 0x12301014 +#define CODE_DATA_PH 0x12301018 +#define ADDR_DATA_PH 0x1230101C +#define ACT_DATA_PH 0x12301020 +// +#define EVENT_VALUE 0x0000beef // ; Code execution complete trigger +#define USER_EVENT0_DATA 0xbadbeef0 +#define USER_EVENT1_DATA 0xbadbeef1 +#define USER_EVENT2_DATA 0xbadbeef2 +#define USER_EVENT3_DATA 0xbadbeef3 +#define USER_EVENT4_DATA 0xbadbeef4 +#define USER_EVENT5_DATA 0xbadbeef5 +#define USER_EVENT6_DATA 0xbadbeef6 +#define USER_EVENT7_DATA 0xbadbeef7 +#define USER_EVENT8_DATA 0xbadbeef8 +#define USER_EVENT9_DATA 0xbadbeef9 +#define USER_EVENT10_DATA 0xbadbeefa +#define USER_EVENT11_DATA 0xbadbeefb +#define USER_EVENT12_DATA 0xbadbeefc +#define USER_EVENT13_DATA 0xbadbeefd +#define USER_EVENT14_DATA 0xbadbeefe +#define USER_EVENT15_DATA 0xbadbeeff +#define MCU_JNT_HALT 0xdeaddead +// +// ;---------------------------------------; +// ; PWM ; +// ; $0020_8000 to $0020_8FFF ; +// ;---------------------------------------; +#define PWM1_BASE_ADDR 0x00208000 +#define PWMC1 PWM1_BASE_ADDR +#define PWMS1 (PWM1_BASE_ADDR+0x04) +#define PWMP1 (PWM1_BASE_ADDR+0x08) +#define PWMCNT1 (PWM1_BASE_ADDR+0x0C) +#define PWMTST1 (PWM1_BASE_ADDR+0x10) + +// ;---------------------------------------; +// ; RAM ; +// ; $0030_0100 to $0031_FFFF ; +// ; $0030_0000 to $0030_00FF for PORTHOLE ; +// ;---------------------------------------; +#define RAM1_BASE_ADDR 0x00300100 +#define RAM1_END_ADDR (RAM1_BASE_ADDR+0x0FF00) +#define RAM2_BASE_ADDR 0x00310000 +#define RAM2_END_ADDR (RAM2_BASE_ADDR+0x10000) +#define TOP_OF_STACK 0x00320000 +// +// ;---------------------------------------; +// ; RTC ; +// ; $0020_4000 to $0020_4FFF ; +// ;---------------------------------------; +#define RTC_BASE_ADDR 0x00204000 +#define RTC_HOURMIN RTC_BASE_ADDR +#define RTC_SECOND (RTC_BASE_ADDR+0x04) +#define RTC_ALRM_HM (RTC_BASE_ADDR+0x08) +#define RTC_ALRM_SEC (RTC_BASE_ADDR+0x0C) +#define RTC_RTCCTL (RTC_BASE_ADDR+0x10) +#define RTC_RTCISR (RTC_BASE_ADDR+0x14) +#define RTC_RTCIENR (RTC_BASE_ADDR+0x18) +#define RTC_STPWCH (RTC_BASE_ADDR+0x1C) +#define RTC_DAYR (RTC_BASE_ADDR+0x20) +#define RTC_DAYALARM (RTC_BASE_ADDR+0x24) +#define RTC_TEST1 (RTC_BASE_ADDR+0x28) +#define RTC_TEST2 (RTC_BASE_ADDR+0x2C) +#define RTC_TEST3 (RTC_BASE_ADDR+0x30) +// +// ;---------------------------------------; +// ; SRAMC ; +// ; $0022_1000 to $0022_1FFF ; +// ;---------------------------------------; +#define SDRAMC_BASE_ADDR 0x00221000 +#define SDRAMC_SDCTL0 SDRAMC_BASE_ADDR +#define SDRAMC_SDCTL1 (SDRAMC_BASE_ADDR+0x04) +// +// ;---------------------------------------; +// ; SIM ; +// ; $0021_1000 to $0021_21FF ; +// ;---------------------------------------; +#define SIM_BASE_ADDR 0x00211000 +#define SIM_PORT_CNTL SIM_BASE_ADDR +#define SIM_CNTL SIM_BASE_ADDR+0x04) +#define SIM_RCV_THRESHOLD SIM_BASE_ADDR+0x08) +#define SIM_ENABLE SIM_BASE_ADDR+0x0C) +#define SIM_XMT_STATUS (SIM_BASE_ADDR+0x10) +#define SIM_RCV_STATUS (SIM_BASE_ADDR+0x14) +#define SIM_INT_MASK (SIM_BASE_ADDR+0x18) +#define SIM_PORT_XMT_BUF (SIM_BASE_ADDR+0x1C) +#define SIM_PORT_RCV_BUF (SIM_BASE_ADDR+0x20) +#define SIM_PORT_DETECT (SIM_BASE_ADDR+0x24) +#define SIM_XMT_THRESHOLD (SIM_BASE_ADDR+0x28) +#define SIM_GUARD_CNTL (SIM_BASE_ADDR+0x2C) +#define SIM_OD_CONFIG (SIM_BASE_ADDR+0x30) +#define SIM_RESET_CNTL (SIM_BASE_ADDR+0x34) +#define SIM_CHAR_WAIT (SIM_BASE_ADDR+0x38) +#define SIM_GPCNT (SIM_BASE_ADDR+0x3C) +#define SIM_DIVISOR (SIM_BASE_ADDR+0x40) +// +// ;---------------------------------------; +// ; TIMER1 ; +// ; $0020_2000 to $0020_2FFF ; +// ;---------------------------------------; +#define TIMER1_BASE_ADDR 0x00202000 +#define TIMER1_TCTL1 TIMER1_BASE_ADDR +#define TIMER1_TPRER1 (TIMER1_BASE_ADDR+0x04) +#define TIMER1_TCMP1 (TIMER1_BASE_ADDR+0x08) +#define TIMER1_TCR1 (TIMER1_BASE_ADDR+0x0C) +#define TIMER1_TCN1 (TIMER1_BASE_ADDR+0x10) +#define TIMER1_TSTAT1 (TIMER1_BASE_ADDR+0x14) + +// ;---------------------------------------; +// ; TIMER2 ; +// ; $0020_3000 to $0020_3FFF ; +// ;---------------------------------------; +#define TIMER2_BASE_ADDR 0x00203000 +#define TIMER2_TCTL2 TIMER2_BASE_ADDR +#define TIMER2_TPRER2 (TIMER2_BASE_ADDR+0x04) +#define TIMER2_TCMP2 (TIMER2_BASE_ADDR+0x08) +#define TIMER2_TCR2 (TIMER2_BASE_ADDR+0x0C) +#define TIMER2_TCN2 (TIMER2_BASE_ADDR+0x10) +#define TIMER2_TSTAT2 (TIMER2_BASE_ADDR+0x14) +// +// ;---------------------------------------; +// ; TUBE ; +// ; CS5 address space ; +// ; $1600_0000 to $16FF_FFFF ; +// ;---------------------------------------; +#define TubeBase 0x16000000 +#define TUBEDataOff 0 // ; Register offsets +#define TUBEDataMask 15 // ; Data +#define CR 13 // ;Carriage return char +#define LF 10 // ;Line Feed char +#define CTRLD 4 // ;Control D char +// +// ;---------------------------------------; +// ; UART1 ; +// ; $0020_6000 to $0020_6FFF ; +// ;---------------------------------------; +#define UART1_BASE_ADDR 0x00206000 +#define UART1_RXDATA UART1_BASE_ADDR +#define UART1_TXDATA (UART1_BASE_ADDR+0x40) +#define UART1_CR1 (UART1_BASE_ADDR+0x80) +#define UART1_CR2 (UART1_BASE_ADDR+0x84) +#define UART1_CR3 (UART1_BASE_ADDR+0x88) +#define UART1_CR4 (UART1_BASE_ADDR+0x8C) +#define UART1_FCR (UART1_BASE_ADDR+0x90) +#define UART1_SR1 (UART1_BASE_ADDR+0x94) +#define UART1_SR2 (UART1_BASE_ADDR+0x98) +#define UART1_ESC (UART1_BASE_ADDR+0x9C) +#define UART1_TIM (UART1_BASE_ADDR+0xA0) +#define UART1_BIR (UART1_BASE_ADDR+0xA4) +#define UART1_BMR (UART1_BASE_ADDR+0xA8) +#define UART1_BRC (UART1_BASE_ADDR+0xAC) +#define UART1_BIPR1 (UART1_BASE_ADDR+0xB0) +#define UART1_BMPR1 (UART1_BASE_ADDR+0xB4) +#define UART1_BIPR2 (UART1_BASE_ADDR+0xB8) +#define UART1_BMPR2 (UART1_BASE_ADDR+0xBC) +#define UART1_BIPR3 (UART1_BASE_ADDR+0xC0) +#define UART1_BMPR3 (UART1_BASE_ADDR+0xC4) +#define UART1_BIPR4 (UART1_BASE_ADDR+0xC8) +#define UART1_BMPR4 (UART1_BASE_ADDR+0xCC) +#define UART1_TS (UART1_BASE_ADDR+0xD0) +// +// ;---------------------------------------; +// ; UART2 ; +// ; $0020_7000 to $0020_7FFF ; +// ;---------------------------------------; +#define UART2_BASE_ADDR 0x00207000 +#define UART2_RXDATA UART2_BASE_ADDR +#define UART2_TXDATA (UART2_BASE_ADDR+0x40) +#define UART2_CR1 (UART2_BASE_ADDR+0x80) +#define UART2_CR2 (UART2_BASE_ADDR+0x84) +#define UART2_CR3 (UART2_BASE_ADDR+0x88) +#define UART2_CR4 (UART2_BASE_ADDR+0x8C) +#define UART2_FCR (UART2_BASE_ADDR+0x90) +#define UART2_SR1 (UART2_BASE_ADDR+0x94) +#define UART2_SR2 (UART2_BASE_ADDR+0x98) +#define UART2_ESC (UART2_BASE_ADDR+0x9C) +#define UART2_TIM (UART2_BASE_ADDR+0xA0) +#define UART2_BIR (UART2_BASE_ADDR+0xA4) +#define UART2_BMR (UART2_BASE_ADDR+0xA8) +#define UART2_BRC (UART2_BASE_ADDR+0xAC) +#define UART2_BIPR1 (UART2_BASE_ADDR+0xB0) +#define UART2_BMPR1 (UART2_BASE_ADDR+0xB4) +#define UART2_BIPR2 (UART2_BASE_ADDR+0xB8) +#define UART2_BMPR2 (UART2_BASE_ADDR+0xBC) +#define UART2_BIPR3 (UART2_BASE_ADDR+0xC0) +#define UART2_BMPR3 (UART2_BASE_ADDR+0xC4) +#define UART2_BIPR4 (UART2_BASE_ADDR+0xC8) +#define UART2_BMPR4 (UART2_BASE_ADDR+0xCC) +#define UART2_TS (UART2_BASE_ADDR+0xD0) + +// ;---------------------------------------; +// ; USBD ; +// ; $0021_2000 to $0021_2FFF ; +// ;---------------------------------------; +#define USBD_BASE_ADDR 0x00212000 +#define USBD_FRAME USBD_BASE_ADDR +#define USBD_SPEC (USBD_BASE_ADDR+0x04) +#define USBD_STAT (USBD_BASE_ADDR+0x08) +#define USBD_CTRL (USBD_BASE_ADDR+0x0C) +#define USBD_DADR (USBD_BASE_ADDR+0x10) +#define USBD_DDAT (USBD_BASE_ADDR+0x14) +#define USBD_INTR (USBD_BASE_ADDR+0x18) +#define USBD_MASK (USBD_BASE_ADDR+0x1C) +#define USBD_MCTL (USBD_BASE_ADDR+0x20) +#define USBD_ENABLE (USBD_BASE_ADDR+0x24) +// +#define USBD_EP0_STAT (USBD_BASE_ADDR+0x30) +#define USBD_EP0_INTR (USBD_BASE_ADDR+0x34) +#define USBD_EP0_MASK (USBD_BASE_ADDR+0x38) +#define USBD_EP0_FDAT (USBD_BASE_ADDR+0x3C) +#define USBD_EP0_FSTAT (USBD_BASE_ADDR+0x40) +#define USBD_EP0_FCTRL (USBD_BASE_ADDR+0x44) +#define USBD_EP0_LFRP (USBD_BASE_ADDR+0x48) +#define USBD_EP0_LFWP (USBD_BASE_ADDR+0x4C) +#define USBD_EP0_FALRM (USBD_BASE_ADDR+0x50) +#define USBD_EP0_FRDP (USBD_BASE_ADDR+0x54) +#define USBD_EP0_FWDP (USBD_BASE_ADDR+0x58) +// +#define USBD_EP1_STAT (USBD_BASE_ADDR+0x60) +#define USBD_EP1_INTR (USBD_BASE_ADDR+0x64) +#define USBD_EP1_MASK (USBD_BASE_ADDR+0x68) +#define USBD_EP1_FDAT (USBD_BASE_ADDR+0x6C) +#define USBD_EP1_FSTAT (USBD_BASE_ADDR+0x70) +#define USBD_EP1_FCTRL (USBD_BASE_ADDR+0x74) +#define USBD_EP1_LFRP (USBD_BASE_ADDR+0x78) +#define USBD_EP1_LFWP (USBD_BASE_ADDR+0x7C) +#define USBD_EP1_FALRM (USBD_BASE_ADDR+0x80) +#define USBD_EP1_FRDP (USBD_BASE_ADDR+0x84) +#define USBD_EP1_FWDP (USBD_BASE_ADDR+0x88) +// +#define USBD_EP2_STAT (USBD_BASE_ADDR+0x90) +#define USBD_EP2_INTR (USBD_BASE_ADDR+0x94) +#define USBD_EP2_MASK (USBD_BASE_ADDR+0x98) +#define USBD_EP2_FDAT (USBD_BASE_ADDR+0x9C) +#define USBD_EP2_FSTAT (USBD_BASE_ADDR+0xA0) +#define USBD_EP2_FCTRL (USBD_BASE_ADDR+0xA4) +#define USBD_EP2_LFRP (USBD_BASE_ADDR+0xA8) +#define USBD_EP2_LFWP (USBD_BASE_ADDR+0xAC) +#define USBD_EP2_FALRM (USBD_BASE_ADDR+0xB0) +#define USBD_EP2_FRDP (USBD_BASE_ADDR+0xB4) +#define USBD_EP2_FWDP (USBD_BASE_ADDR+0xB8) +// +#define USBD_EP3_STAT (USBD_BASE_ADDR+0xC0) +#define USBD_EP3_INTR (USBD_BASE_ADDR+0xC4) +#define USBD_EP3_MASK (USBD_BASE_ADDR+0xC8) +#define USBD_EP3_FDAT (USBD_BASE_ADDR+0xCC) +#define USBD_EP3_FSTAT (USBD_BASE_ADDR+0xD0) +#define USBD_EP3_FCTRL (USBD_BASE_ADDR+0xD4) +#define USBD_EP3_LFRP (USBD_BASE_ADDR+0xD8) +#define USBD_EP3_LFWP (USBD_BASE_ADDR+0xDC) +#define USBD_EP3_FALRM (USBD_BASE_ADDR+0xE0) +#define USBD_EP3_FRDP (USBD_BASE_ADDR+0xE4) +#define USBD_EP3_FWDP (USBD_BASE_ADDR+0xE8) +// +#define USBD_EP4_STAT (USBD_BASE_ADDR+0xF0) +#define USBD_EP4_INTR (USBD_BASE_ADDR+0xF4) +#define USBD_EP4_MASK (USBD_BASE_ADDR+0xF8) +#define USBD_EP4_FDAT (USBD_BASE_ADDR+0xFC) +#define USBD_EP4_FSTAT (USBD_BASE_ADDR+0x100) +#define USBD_EP4_FCTRL (USBD_BASE_ADDR+0x104) +#define USBD_EP4_LFRP (USBD_BASE_ADDR+0x108) +#define USBD_EP4_LFWP (USBD_BASE_ADDR+0x10C) +#define USBD_EP4_FALRM (USBD_BASE_ADDR+0x110) +#define USBD_EP4_FRDP (USBD_BASE_ADDR+0x114) +#define USBD_EP4_FWDP (USBD_BASE_ADDR+0x118) +#define USBD_EP5_STAT (USBD_BASE_ADDR+0x120) +#define USBD_EP5_INTR (USBD_BASE_ADDR+0x124) +#define USBD_EP5_MASK (USBD_BASE_ADDR+0x128) +#define USBD_EP5_FDAT (USBD_BASE_ADDR+0x12C) +#define USBD_EP5_FSTAT (USBD_BASE_ADDR+0x130) +#define USBD_EP5_FCTRL (USBD_BASE_ADDR+0x134) +#define USBD_EP5_LFRP (USBD_BASE_ADDR+0x138) +#define USBD_EP5_LFWP (USBD_BASE_ADDR+0x13C) +#define USBD_EP5_FALRM (USBD_BASE_ADDR+0x140) +#define USBD_EP5_FRDP (USBD_BASE_ADDR+0x144) +#define USBD_EP5_FWDP (USBD_BASE_ADDR+0x148) +// +// ;---------------------------------------; +// ; CSPI_2 ; +// ; $0021_9000 to $0021_9FFF ; +// ;---------------------------------------; +#define CSPI_2_BASE_ADDR 0x00219000 +#define CSPI_2_SPIRXD CSPI_2_BASE_ADDR +#define CSPI_2_SPITXD (CSPI_2_BASE_ADDR+0x04) +#define CSPI_2_SPICONT1 (CSPI_2_BASE_ADDR+0x08) +#define CSPI_2_INTCS (CSPI_2_BASE_ADDR+0x0C) +#define CSPI_2_SPITEST (CSPI_2_BASE_ADDR+0x10) +#define CSPI_2_SPISPCR (CSPI_2_BASE_ADDR+0x14) +#define CSPI_2_SPIDMA (CSPI_2_BASE_ADDR+0x18) +#define CSPI_2_SPIRESET (CSPI_2_BASE_ADDR+0x1C) +// +// ;---------------------------------------; +// ; WDT ; +// ; $0020_1000 to $0020_1FFF ; +// ;---------------------------------------; +#define WDOG_BASE_ADDR 0x00201000 +#define WDOG_WCR WDOG_BASE_ADDR +#define WDOG_WSR (WDOG_BASE_ADDR+0x04) +#define WDOG_WSTR (WDOG_BASE_ADDR+0x08) + +// ;---------------------------------------; +// ; WEIM ; +// ; $0022_0000 to $0022_0FFF ; +// ;---------------------------------------; +#define EIM_BASE_ADDR (DBMX1_BASE+0x00220000) +#define EIM_CS0H EIM_BASE_ADDR +#define EIM_CS0L (EIM_BASE_ADDR+0x04) +#define EIM_CS1H (EIM_BASE_ADDR+0x08) +#define EIM_CS1L (EIM_BASE_ADDR+0x0C) +#define EIM_CS2H (EIM_BASE_ADDR+0x10) +#define EIM_CS2L (EIM_BASE_ADDR+0x14) +#define EIM_CS3H (EIM_BASE_ADDR+0x18) +#define EIM_CS3L (EIM_BASE_ADDR+0x1C) +#define EIM_CS4H (EIM_BASE_ADDR+0x20) +#define EIM_CS4L (EIM_BASE_ADDR+0x24) +#define EIM_CS5H (EIM_BASE_ADDR+0x28) +#define EIM_CS5L (EIM_BASE_ADDR+0x2C) +#define EIM (EIM_BASE_ADDR+0x30) +// +// ;---------------------------------------; +// ; WEIM ; +// ; $0022_0000 to $0022_0FFF ; +// ;---------------------------------------; +// ; External Memory address (64M Bytes each) +// ; +#define CSD0_BASE_ADDR 0x08000000 // ; SDRAM +#define CSD0_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF) +#define CSD1_BASE_ADDR 0x0C000000 // ; SDRAM +#define CSD1_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF) +#define CS0_BASE_ADDR 0x10000000 // ; CS0 +#define CS0_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF) +#define CS1_BASE_ADDR 0x12000000 // ; CS1 +#define CS1_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF) +#define CS2_BASE_ADDR 0x13000000 // ; CS2 +#define CS2_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF) +#define CS3_BASE_ADDR 0x14000000 // ; CS3 +#define CS3_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF) +#define CS4_BASE_ADDR 0x15000000 // ; CS4 +#define CS4_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF) +#define CS5_BASE_ADDR 0x16000000 // ; CS5 +#define CS5_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF) +// +// ;---------------------------------------; +// ; SDRAMC ; +// ; $0022_0000 to $0022_0FFF ; +// ;---------------------------------------; +// +#define SDRAM0_BASE 0x08000000 +#define SDRAM1_BASE 0x0C000000 +#define SDRAM0_END_ADDR 0x08FFFF00 +#define SDRAM1_END_ADDR 0x0CFFFF00 + +#endif diff -Nru src.org/drivers/mx1mmc/Makefile src/drivers/mx1mmc/Makefile --- src.org/drivers/mx1mmc/Makefile Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/Makefile Tue Sep 27 03:09:55 2005 @@ -0,0 +1,45 @@ +# +# Makefile for the MX1 MMC driver. +# + +# Subdirs. + +SUB_DIRS := +MOD_SUB_DIRS := $(SUB_DIRS) +MOD_IN_SUB_DIRS := $(SUB_DIRS) +ALL_SUB_DIRS := $(SUB_DIRS) + +# The target object and module list name. + +O_TARGET := mmc.o +M_OBJS := +O_OBJS := + +# Objects that export symbols. + +#export-objs := mmc.o + +# Object file lists. + +obj-y := +obj-m := +obj-n := +obj- := + +# Object file lists. + +obj-$(CONFIG_MX1_MMC) += mmc_main.o mmc_drv.o mmc_cmd.o mmc_io.o + +# Files that are both resident and modular: remove from modular. + +obj-m := $(filter-out $(obj-y), $(obj-m)) +int-m := $(filter-out $(int-y), $(int-m)) + +# Translate to Rules.make lists. + +O_OBJS := $(sort $(filter-out $(export-objs), $(obj-y))) +OX_OBJS := $(sort $(filter $(export-objs), $(obj-y))) +M_OBJS := $(sort $(filter-out $(export-objs), $(obj-m))) +MX_OBJS := $(sort $(filter $(export-objs), $(obj-m))) + +include $(TOPDIR)/Rules.make diff -Nru src.org/drivers/mx1mmc/dbmx1_dma.h src/drivers/mx1mmc/dbmx1_dma.h --- src.org/drivers/mx1mmc/dbmx1_dma.h Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/dbmx1_dma.h Fri Sep 23 20:26:30 2005 @@ -0,0 +1,58 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2002 Motorola Semiconductors HK Ltd + * + */ + +/****************************************************************************** + * + * Copyright (C) 2001, Motorola All Rights Reserved + * + * File Name: dbmx1_dma.h + * + * Progammers: Yiwei Zhao + * + * Date of Creations: 30 Nov 2001 + * + * Synopsis: + * + * Modification History: + * 30 Nov, 2001, initialization version + * + ******************************************************************************/ +#ifndef DBMX1_DMA +#define DBMX1_DMA + +/*regsiters for dma*/ + +//#define _reg_DMA_DIMR (*((volatile unsigned long *)(IO_ADDRESS(0x209008)))) +/*dma transmitting*/ + +#define _reg_DMA_SAR(channum) (*((volatile unsigned long *)(IO_ADDRESS((0x209080 + channum * 0x40))))) +#define _reg_DMA_DAR(channum) (*((volatile unsigned long *)(IO_ADDRESS((0x209084 + channum * 0x40))))) +#define _reg_DMA_CNTR(channum) (*((volatile unsigned long *)(IO_ADDRESS((0x209088 + channum * 0x40))))) +#define _reg_DMA_CCR(channum) (*((volatile unsigned long *)(IO_ADDRESS((0x20908C + channum * 0x40))))) +#define _reg_DMA_RSSR(channum) (*((volatile unsigned long *)(IO_ADDRESS((0x209090 + channum * 0x40))))) +#define _reg_DMA_BLR(channum) (*((volatile unsigned long *)(IO_ADDRESS((0x209094 + channum * 0x40))))) +#define _reg_DMA_RTOR(channum) (*((volatile unsigned long *)(IO_ADDRESS((0x209098 + channum * 0x40))))) +#define _reg_DMA_BUCR(channum) (*((volatile unsigned long *)(IO_ADDRESS((0x20909C + channum * 0x40))))) + +//typedef void (*callback_t)(void); +//typedef void (*err_callback_t)(int error_type); + +void request_dma_intr(unsigned int channel,void (* mmcsd_dma_isr)(void),void (*mmcsd_dma_err_isr)(int)); + +#endif diff -Nru src.org/drivers/mx1mmc/dbmx1_type.h src/drivers/mx1mmc/dbmx1_type.h --- src.org/drivers/mx1mmc/dbmx1_type.h Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/dbmx1_type.h Fri Sep 23 20:26:30 2005 @@ -0,0 +1,55 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2002 Motorola Semiconductors HK Ltd + * + */ + +/****************************************************************************** + * + * Copyright (C) 2001, Motorola All Rights Reserved + * + * File Name: dbmx1_type.h + * + * Progammers: Yiwei Zhao + * + * Date of Creations: 30 Nov 2001 + * + * Synopsis: + * + * Modification History: + * 30 Nov, 2001, initialization version + * + ******************************************************************************/ +#ifndef DBMX1_TYPES +#define DBMX1_TYPES + +typedef signed char BOOLEAN; +typedef unsigned char UINT8; /* Unsigned 8 bit quantity */ +typedef signed char SINT8; /* Signed 8 bit quantity */ +typedef unsigned short UINT16; /* Unsigned 16 bit quantity */ +typedef signed short SINT16; /* Signed 16 bit quantity */ +typedef unsigned long UINT32; /* Unsigned 32 bit quantity */ +typedef signed long SINT32; /* Signed 32 bit quantity */ + +typedef volatile BOOLEAN VBOOLEAN; +typedef volatile UINT8 VUINT8; /* Unsigned 8 bit quantity */ +typedef volatile SINT8 VSINT8; /* Signed 8 bit quantity */ +typedef volatile UINT16 VUINT16; /* Unsigned 16 bit quantity */ +typedef volatile SINT16 VSINT16; /* Signed 16 bit quantity */ +typedef volatile UINT32 VUINT32; /* Unsigned 32 bit quantity */ +typedef volatile SINT32 VSINT32; /* Signed 32 bit quantity */ + +#endif diff -Nru src.org/drivers/mx1mmc/mmc_cmd.c src/drivers/mx1mmc/mmc_cmd.c --- src.org/drivers/mx1mmc/mmc_cmd.c Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/mmc_cmd.c Fri Sep 30 20:55:23 2005 @@ -0,0 +1,937 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2002 Motorola Semiconductors HK Ltd + * + */ + +/****************************************************************************** + * + * Copyright (C) 2001, Motorola All Rights Reserved + * + * File Name: mmcsd_cmd.c + * + * Progammers: Yiwei Zhao + * + * Date of Creations: 30 DEC,2001 + * + * Synopsis: + * + * Modification History: + * 30 DEC, 2001 + * + *****************************************************************************/ + +#include "dbmx1_type.h" +#include "mmc_def.h" +#include "mmc_main.h" + +/* Functions List: + * + */ + +/****************************************************************************** + * Function Name: _MMCSD_GoIdleState + * + * Input: None. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * Resets all cards to idle state + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +MMCSD_STATUS _MMCSD_GoIdleState(int port) +{ + MMCSD_STATUS ret; + ret=_MMCSD_NoDataCommand(MMCSD_CMD0,0,MMCSDB_INIT,port); + return ret; +} + +/****************************************************************************** + * Function Name: _MMCSD_SendOpCond + * + * Input: + * voltage + * + * Value Returned: + * + * Description: + * Ask all cards in idle state to send their operation conditions register + * contern in response on the CMD line. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +MMCSD_STATUS _MMCSD_SendOpCond(u32 voltage,int port) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + + // Try first for a SD card + ret = _MMCSD_NoDataCommand(MMCSD_CMD55, 0, MMCSDB_R1, port); + + if (ret == 0) + { + // Read response of CMD55 + _MMCSD_GetResponses(&rp, MMCSDB_R1, port); + + g_mmcsd_devices[port].card_type = MMCSD_TYPE_SD; + ret = _MMCSD_NoDataCommand(MMCSD_ACMD41, voltage, MMCSDB_R3, port); + } + else + { + g_mmcsd_devices[port].card_type = MMCSD_TYPE_MMC; + + //voltage = 0xFFFFFF0; + ret = _MMCSD_NoDataCommand(MMCSD_CMD1, voltage, MMCSDB_R3, port); + } + + _MMCSD_GetResponses(&rp, MMCSDB_R3, port); + + if (ret) + { + TRACE("CMD1 failed with ret = 0x%lx",ret); + return ret; + } + + + if ((rp.OCR & 0x80000000) == 0) + return MMCSD_CARD_BUSY; + else + { + //TRACE("OCR is %lx",rp.OCR); + return 0; + } + +} + +/****************************************************************************** + * Function Name: _MMCSD_AllSendCID + * + * Input: + * UINT8 * pCidBuff + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * CMD2: Ask all cards to send their CID numbers on rhe CMD line + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +/***************************************************************************** + + CID Register:(Bit) 127 119 111 103 95 87 79 71 63 55 47 39 31 15 7 0 + ------------------------------------------------------------------------------------------ + CID Register |MID | OID | PNM | PSN |MDT| CRC| + ------------------------------------------------------------------------------------------- +pCidBuff :(BYTE) | 0 | 1 | 2 | 4 | 5 | 7 | 8 | 9 | 10| 11| 12|13| 14 | 15 | 16| + + + ******************************************************************************/ +MMCSD_STATUS _MMCSD_AllSendCID(u8 *pCidBuff,int port) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + int i; + + ret=_MMCSD_NoDataCommand(MMCSD_CMD2,0,MMCSDB_R2,port); + + if(ret) + { + FAILED("Command 2 returns with %ld",ret); + return ret; + } + + _MMCSD_GetResponses(&rp,MMCSDB_R2,port); + + for(i=0;i<16;i++) + { + pCidBuff[i]=rp.CID[i]; + } + return 0; +} + +/****************************************************************************** + * Function Name: _MMCSD_SetRelativeAddr + * + * Input: + * addr relative address + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * Assigns relative address to the card + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + * + * Qeustion: + * + * assigned or generated by itself? + * + *****************************************************************************/ +MMCSD_STATUS _MMCSD_SetRelativeAddr(u32 *addr, int port) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + + ret = _MMCSD_NoDataCommand( + MMCSD_CMD3, + (g_mmcsd_devices[port].card_type == MMCSD_TYPE_MMC) ? *addr << 16 : 0, + MMCSDB_R1, + port); + + if (ret) + return ret; + + _MMCSD_GetResponses(&rp, MMCSDB_R1, port); + + if (g_mmcsd_devices[port].card_type == MMCSD_TYPE_SD) + { + *addr = (rp.status >> 16) & 0xFFFF; + return 0; + } + else + return rp.status & MMCSD_STATUS_NOERROR; +} + +/****************************************************************************** + * Function Name: _MMCSD_SelectDeselectCard + * + * Input: + * + * addr: relative address + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS _MMCSD_SelectDeselectCard(u32 addr,u32 port) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + + if(addr!=0) + ret=_MMCSD_NoDataCommand(MMCSD_CMD7,addr<<16,0x40|MMCSDB_R1,port); + else + ret=_MMCSD_NoDataCommand(MMCSD_CMD7,0,0x40,port); + + if(ret) + return ret; + + _MMCSD_GetResponses(&rp,MMCSDB_R1,port); + + + return rp.status&MMCSD_STATUS_NOERROR; + +} + +/****************************************************************************** + * Function Name: _MMCSD_SendCSD + * + * Input: + * addr: relative address. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * CMD9: Addressed card sends its card-specific data(CSD) + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +/***************************************************************************** + + CSD Register + ----------------------------------------------------------------------------- + Name | Width| CSD_Slice| pCsdbuff (BYTE) + ----------------------------------------------------------------------------- + CSD struction 2 127:126 + System spec. version 4 125:122 0 + reserved 2 121:120 + ----------------------------------------------------------------------------- + data read access time 1 8 119:112 1 + ----------------------------------------------------------------------------- + data read access time 2 8 111:104 2 + ----------------------------------------------------------------------------- + Max data transfer rate 8 103:96 3 + ----------------------------------------------------------------------------- + card command classes 12 95:84 4 + max read data block length 4 83:80 5 + ------------------------------------------------------------------------------ + partial blocks for read length 1 79:79 + wirte block misalignment 1 78:78 + read block misalignment 1 77:77 + DSR implemented 1 76:76 + reserved 2 75:74 + device size 12 73:62 6-7 + max read current 3 61:69 + max read current 3 58-56 8 + ------------------------------------------------------------------------------ + max write current 3 55-53 + max write current 3 52-50 + device size multiplier 3 49-47 9 + erase sector size 5 46-42 + erase group size 5 41-37 10 + write protect group size 5 36-32 11 + ------------------------------------------------------------------------------ + write protect group enable 1 31:31 + manufactuter default ECC 2 30:29 + write speed factor 3 28:26 + max. write data block length 4 25:22 12 + partial blocks for write allowed 1 21:21 + reserved 5 20:16 13 + ------------------------------------------------------------------------------ + File format group 1 15:15 + copy flag 1 14:14 + permanent write protection 1 13:13 + temporary write protection 1 12:12 + file format 2 11:10 + ECC code 2 9:8 14 + -------------------------------------------------------------------------------- + CRC 7 7:1 + Not used always '1' 1 0:0 15 + ------------------------------------------------------------------------------- + + ******************************************************************************/ +MMCSD_STATUS _MMCSD_SendCSD(u32 addr,u8* pBuff,u32 port) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + int i; + + ret=_MMCSD_NoDataCommand(MMCSD_CMD9,addr<<16,MMCSDB_R2,port); + + if(ret) + return ret; + + _MMCSD_GetResponses(&rp,MMCSDB_R2,port); + + for(i=0;i<16;i++) + { + pBuff[i]=rp.CSD[i]; + TRACE(" %02x", pBuff[i]); + } + + return 0; +} + +/****************************************************************************** + * Function Name: _MMCSD_SendCID + * + * Input: + * addr: relative address. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * CMD10: Addressed card sends its card-specific data(CSD) + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS _MMCSD_SendCID(u32 addr,u8 * pBuff,u32 port) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + int i; + + ret=_MMCSD_NoDataCommand(MMCSD_CMD10,addr<<16,MMCSDB_R2,port); + + if(ret) + return ret; + + _MMCSD_GetResponses(&rp,MMCSDB_R2,port); + for(i=0;i<16;i++) + { + pBuff[i]=rp.CID[i]; + } + + return 0; +} + +/****************************************************************************** + * Function Name: _MMCSD_SendStatus + * + * Input: . + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: CMD13 addressed card sends its status register + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS _MMCSD_SendStatus(u32 addr,u32 *pStatus,u32 port) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + + ret=_MMCSD_NoDataCommand(MMCSD_CMD13,addr<<16,MMCSDB_R1,port); + if(ret) + { + //FAILED("CMD13 Failed with ret = 0x%x",ret); + *pStatus = ret; + return ret; + } + + _MMCSD_GetResponses(&rp,MMCSDB_R1,port); + + *pStatus=rp.status; + + return ((rp.status)&MMCSD_STATUS_NOERROR); + +} + +/****************************************************************************** + * Function Name: _MMCSD_SetBlockLen + * + * Input: None. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS _MMCSD_SetBlockLen(u32 size, u32 num,u32 port) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + + _MMCSD_SetBlockLenReg(size,port); + _MMCSD_SetNumberOfBlockReg(num,port); + + ret=_MMCSD_NoDataCommand(MMCSD_CMD16,size,MMCSDB_R1,port); + + if(ret) + { + FAILED("setBlockLen ret= %x \n",ret); + return ret; + } + _MMCSD_GetResponses(&rp,MMCSDB_R1,port); + + return rp.status&MMCSD_STATUS_NOERROR; +} + +/****************************************************************************** + * Function Name: _MMCSD_TagSectorStart + * + * Input: U32 addr address + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * CMD33 Sets the address of the first sector of the erase group + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS _MMCSD_TagSectorStart(u32 addr) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + + ret=_MMCSD_NoDataCommand(MMCSD_CMD32,addr,MMCSDB_R1,0); + + if(ret) + return ret; + + _MMCSD_GetResponses(&rp,MMCSDB_R1,0); + + return rp.status&MMCSD_STATUS_NOERROR; + +} +/****************************************************************************** + * Function Name: _MMCSD_TagSectorEnd + * + * Input: U32 addr address + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * CMD33 Sets the address of the last sector of the erase group + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +MMCSD_STATUS _MMCSD_TagSectorEnd(u32 addr) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + + ret=_MMCSD_NoDataCommand(MMCSD_CMD33,addr,MMCSDB_R1,0); + + + if(ret) + return ret; + + _MMCSD_GetResponses(&rp,MMCSDB_R1,0); + + return rp.status&MMCSD_STATUS_NOERROR; + +} + +/****************************************************************************** + * Function Name: _MMCSD_Erase + * + * Input: + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * Erase all previous selected blocks. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS _MMCSD_Erase() +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + + ret=_MMCSD_NoDataCommand(MMCSD_CMD38,0,MMCSDB_R1,0); + + if(ret) + return ret; + + _MMCSD_GetResponses(&rp,MMCSDB_R1,0); + + + return rp.status&MMCSD_STATUS_NOERROR; + +} + +/****************************************************************************** + * Function Name: _MMCSD_NoDataCommand + * + * Input: + * cmd Command Number + * arg Command argument + * ctrl Command control value inculding response type + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * Send commend to MMC card and wait for response + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +extern u8 g_mmcsd_cmd[2]; + +MMCSD_STATUS _MMCSD_NoDataCommand(u8 cmd, u32 arg,u32 ctrl,int port) +{ + MMCSD_STATUS ret; + u32 int_mask; + int timeout = 100; + + + switch(cmd) + { + case MMCSD_CMD16: + timeout =50 ; + break; + + case MMCSD_CMD6: + timeout = 3; + break; + + case MMCSD_CMD25: + timeout = 50; + break; + case MMCSD_CMD38: + timeout = 100*60*5; + break; + default : + timeout = 100; + + } + g_mmcsd_cmd[port] = cmd; + _MMCSD_Mask_interrupt(0x7b,&int_mask,port); + + _MMCSD_StopClk(port); + _MMCSD_SetCmd(cmd,arg,ctrl,port); + _MMCSD_StartClk(port); + if((cmd==MMCSD_CMD13)||(cmd==MMCSD_CMD55)) + { + ret=_MMCSD_WaitUntil(MMCSD_CMD_DONE,port); + } + else + { + ret=_MMCSD_irq_WaitUntil(MMCSD_CMD_DONE,cmd,timeout,port); + } + + _MMCSD_Restore_Mask(int_mask,port); + + return ret; +} + +MMCSD_STATUS _MMCSD_irq_WaitUntil(u32 EndCondition,u8 cmd,int timeout,int port) +{ + + MMCSD_Dev *device; + u32 status,timeleft; + + device = g_selected_lock[port].device; + + if(device==NULL) + { //polling + //TRACE("device is NULL"); + do + { +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + status = mmcsdr_status_2; + else + status = mmcsdr_status; +#endif +#ifdef CONFIG_ARCH_MX1ADS + status = mmcsdr_status; +#endif + } + while ((status&0x2002)==0); + + if(status&MMCSD_CMD_TIMEOUT) + { +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + { + FAILED("CMD Result: 0x%lx",mmcsdr_status_2); + } + else + { + FAILED("CMD Result: 0x%lx",mmcsdr_status); + } +#endif +#ifdef CONFIG_ARCH_MX1ADS + FAILED("CMD Result: 0x%lx",mmcsdr_status); +#endif + } + + return (status&MMCSD_CMD_TIMEOUT); + } + +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + status = mmcsdr_status_2; // Sometimes, the interrupt has happened. + else + status = mmcsdr_status; // Sometimes, the interrupt has happened. +#endif +#ifdef CONFIG_ARCH_MX1ADS + status = mmcsdr_status; // Sometimes, the interrupt has happened. +#endif + + if((status&(MMCSD_STATUS_ERR|MMCSD_END_CMD_RESP))==0) + { + timeleft = interruptible_sleep_on_timeout(&(device->select_wait),timeout); + if(!timeleft) + { +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + status = mmcsdr_status_2; // Sometimes, the interrupt has happened. + else + status = mmcsdr_status; // Sometimes, the interrupt has happened. +#endif +#ifdef CONFIG_ARCH_MX2ADS + status = mmcsdr_status; // Sometimes, the interrupt has happened. +#endif + if((status&(MMCSD_STATUS_ERR|MMCSD_END_CMD_RESP))==0) + { + FAILED("Time Out, mmcsdr_status = 0x%lx, cmd%d",(unsigned long)status,cmd); + return MMCSD_ERROR; + } + TRACE("Time Out!,cmd%d",cmd); + } + else + { + status = device->result; + } + } + if(status&MMCSD_STATUS_ERR) + { + //FAILED("error, status is 0x%0lX,(cmd%d) ",status,cmd); + return(status&MMCSD_STATUS_ERR); + } + + if(EndCondition == MMCSD_CMD_DONE) + { + if((status&MMCSD_END_CMD_RESP)==0) + { + FAILED("error, status is 0x%0lX,(cmd%d)",(unsigned long)status,cmd); + return(MMCSD_ERROR); + } + } + + return (MMCSD_OK); + +} + +void _MMCSD_Mask_interrupt(u32 mask, u32 *orig, int port) +{ +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + { + *orig = mmcsdr_int_mask_2; + mmcsdr_int_mask_2 = mask; + TRACE("Int_mask is 0x%0X",(unsigned long)mmcsdr_int_mask_2); + } + + else + { + *orig = mmcsdr_int_mask; + mmcsdr_int_mask = mask; + TRACE("Int_mask is 0x%0X",(unsigned long)mmcsdr_int_mask); + } +#endif +#ifdef CONFIG_ARCH_MX1ADS + *orig = mmcsdr_int_mask; + mmcsdr_int_mask = mask; + TRACE("Int_mask is 0x%0X",(unsigned long)mmcsdr_int_mask); +#endif +} +void _MMCSD_Restore_Mask(u32 orig,int port) +{ +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + mmcsdr_int_mask_2 = orig; + else + mmcsdr_int_mask = orig; +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_int_mask = orig; +#endif + // TRACE("*mmcsdr_int_mask = 0x%x",*mmcsdr_int_mask); +} + +/****************************************************************************** + * Function Name: _MMCSD_WaitUntil + * + * Input: + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * Wait until Command done + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS _MMCSD_WaitUntil(u32 EndCondition,int port) +{ + //waiting for the End Cmd Response + volatile u32 status; + u32 counter = 0xFFFFFFFF; + + do{ +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + status = mmcsdr_status_2; + else + status = mmcsdr_status; +#endif +#ifdef CONFIG_ARCH_MX1ADS + status = mmcsdr_status; +#endif + + counter--; + if(counter==0) + { + TRACE("Time Out."); + return MMCSD_ERROR; + } + //TRACE("staus is %lx",status); + } + while ((status&(MMCSD_END_CMD_RESP|MMCSD_STATUS_ERR))==0); + +#ifdef CONFIG_ARCH_MX2ADS + if(status&(MMCSD_READ_TIMEOUT|MMCSD_WRITE_CRC) != 0) + { + if(port == 1) + { + FAILED(" CMD Result: 0x%lx",mmcsdr_status_2); + } + else + { + FAILED(" CMD Result: 0x%lx",mmcsdr_status); + } + } + + return (status&(MMCSD_READ_TIMEOUT|MMCSD_WRITE_CRC)); +#endif +#ifdef CONFIG_ARCH_MX1ADS + if(status&MMCSD_STATUS_ERR) + FAILED(" CMD Result: 0x%lx",mmcsdr_status); + return (status&MMCSD_STATUS_ERR); +#endif + +} + +/****************************************************************************** + * Function Name: _MMCSD_SetWriteProt + * + * Input: + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * this routine will set the write protection bit for the addressed + * group. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS _MMCSD_SetWriteProt(u32 addr) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + + ret=_MMCSD_NoDataCommand(MMCSD_CMD28,addr,MMCSDB_R1,0); + + if(ret) + return ret; + + _MMCSD_GetResponses(&rp,MMCSDB_R1,0); + + + return rp.status&MMCSD_STATUS_NOERROR; + +} +/****************************************************************************** + * Function Name: _MMCSD_ClearWriteProt + * + * Input: + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * This routine will clear the write protection bit for the addressed + * group. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS _MMCSD_ClearWriteProt(u32 addr) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + + ret=_MMCSD_NoDataCommand(MMCSD_CMD29,addr,MMCSDB_R1,0); + + if(ret) + return ret; + + _MMCSD_GetResponses(&rp,MMCSDB_R1,0); + + + return rp.status&MMCSD_STATUS_NOERROR; + +} + +MMCSD_STATUS _MMCSD_SetBusWidth(u32 rca, u32 width,u32 port) +{ + MMCSD_Responses rp; + MMCSD_STATUS ret; + u32 para; + + //TRACE("Set Bus Width =%d",width); + ret=_MMCSD_NoDataCommand(MMCSD_CMD55,rca<<16,MMCSDB_R1,port); + if(ret) + { + TRACE("CMD55 failed with ret = 0x%lx",ret); + return ret; + } + _MMCSD_GetResponses(&rp,MMCSDB_R1,port); + + // para = (rca<<16)|width; + para = width; + ret=_MMCSD_NoDataCommand(MMCSD_ACMD6,para,MMCSDB_R1,port); + if(ret) + { + TRACE("ACMD6 failed with ret = 0x%lx",ret); + return ret; //meet some error + } + + _MMCSD_GetResponses(&rp,MMCSDB_R1,port); + + return MMCSD_OK; +} +/* + MMCSD_STATUS _MMCSD_SendSCR(UINT32 rca,MMCSD_Responses *rp) + { + MMCSD_STATUS ret; + + ret=_MMCSD_NoDataCommand(MMCSD_CMD55,rca<<16,MMCSDB_R1); + if(ret) + { + FAILED("CMD55 failed with ret = 0x%lx",ret); + return ret; + } + _MMCSD_GetResponses(rp,MMCSDB_R1); + + ret=_MMCSD_NoDataCommand(MMCSD_ACMD51,0,MMCSDB_R1); + if(ret) + { + FAILED("ACMD6 failed with ret = 0x%lx",ret); + return ret; //meet some error + } + + _MMCSD_GetResponses(rp,MMCSDB_R1); + + return MMCSD_OK; + } + */ diff -Nru src.org/drivers/mx1mmc/mmc_def.h src/drivers/mx1mmc/mmc_def.h --- src.org/drivers/mx1mmc/mmc_def.h Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/mmc_def.h Wed Oct 12 23:09:11 2005 @@ -0,0 +1,375 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2002 Motorola Semiconductors HK Ltd + * + */ + + +#ifndef MMCSDLOCAL_H_adkf /* PROTECT DOUBLE INCLUDE */ +#define MMCSDLOCAL_H_adkf +#include +#ifdef CONFIG_ARCH_MX2ADS +#include +#endif + + +#define MMCSD_TYPE_MMC 1 +#define MMCSD_TYPE_SD 2 + +//define Mmc Request Source , see I/O channel request source select register +#define MMCSD_REQUEST_SOURCE 21 + + + +/*--------------------------------------------------------------------------*/ +/* DEFINITIONS FOR CSD/CID */ +/*--------------------------------------------------------------------------*/ +#define MMCSD_CSD_LEN 0x0080 /* BIT LENGTH OF CSD REGISTER */ +#define MMCSD_CID_LEN 0x0080 /* BIT LENGTH OF CID REGISTER */ +#define MMCSD_CSD_BYTESIZE 16 /* BYTE LENGTH OF CSD REGISTER*/ +#define MMCSD_CID_BYTESIZE 16 /* BYTE LENGTH OF CID REGISTER*/ + + +/*--------------------------------------------------------------------------*/ +/* DEFINE COMMANDS */ +/*--------------------------------------------------------------------------*/ +#define MMCSD_CMD0 0x00 +#define MMCSD_CMD1 0x01 +#define MMCSD_CMD2 0x02 +#define MMCSD_CMD3 0x03 +#define MMCSD_CMD4 0x04 +#define MMCSD_CMD5 0x05 +#define MMCSD_CMD6 0x06 +#define MMCSD_CMD7 0x07 +#define MMCSD_CMD8 0x08 +#define MMCSD_CMD9 0x09 +#define MMCSD_CMD10 0x0A +#define MMCSD_CMD11 0x0B +#define MMCSD_CMD12 0x0C +#define MMCSD_CMD13 0x0D +#define MMCSD_CMD14 0x0E +#define MMCSD_CMD15 0x0F +#define MMCSD_CMD16 0x10 +#define MMCSD_CMD17 0x11 +#define MMCSD_CMD18 0x12 +#define MMCSD_CMD19 0x13 +#define MMCSD_CMD20 0x14 +#define MMCSD_CMD21 0x15 +#define MMCSD_CMD22 0x16 +#define MMCSD_CMD23 0x17 +#define MMCSD_CMD24 0x18 +#define MMCSD_CMD25 0x19 +#define MMCSD_CMD26 0x1A +#define MMCSD_CMD27 0x1B +#define MMCSD_CMD28 0x1C +#define MMCSD_CMD29 0x1D +#define MMCSD_CMD30 0x1E +#define MMCSD_CMD31 0x1F +#define MMCSD_CMD32 0x20 +#define MMCSD_CMD33 0x21 +#define MMCSD_CMD34 0x22 +#define MMCSD_CMD35 0x23 +#define MMCSD_CMD36 0x24 +#define MMCSD_CMD37 0x25 +#define MMCSD_CMD38 0x26 +#define MMCSD_CMD39 0x27 +#define MMCSD_CMD40 0x28 +#define MMCSD_CMD41 0x29 +#define MMCSD_CMD42 0x2A +#define MMCSD_CMD43 0x2B +#define MMCSD_CMD44 0x2C +#define MMCSD_CMD45 0x2D +#define MMCSD_CMD46 0x2E +#define MMCSD_CMD47 0x2F +#define MMCSD_CMD48 0x30 +#define MMCSD_CMD49 0x31 +#define MMCSD_CMD50 0x32 +#define MMCSD_CMD51 0x33 +#define MMCSD_CMD52 0x34 +#define MMCSD_CMD53 0x35 +#define MMCSD_CMD54 0x36 +#define MMCSD_CMD55 0x37 +#define MMCSD_CMD56 0x38 +#define MMCSD_CMD57 0x39 +#define MMCSD_CMD58 0x3A +#define MMCSD_CMD59 0x3B +#define MMCSD_CMD60 0x3C +#define MMCSD_CMD61 0x3D +#define MMCSD_CMD62 0x3E +#define MMCSD_CMD63 0x3F + +#define MMCSD_ACMD6 0x06 +#define MMCSD_ACMD13 0x0D +#define MMCSD_ACMD22 0x16 +#define MMCSD_ACMD23 0x17 +#define MMCSD_ACMD41 0x29 +#define MMCSD_ACMD42 0x2A +#define MMCSD_ACMD51 0x33 + +#define MMCSD_CCC_BASIC (0x1) +#define MMCSD_CCC_RES1 (0x1<<1) +#define MMCSD_CCC_BLKRD (0x1<<2) +#define MMCSD_CCC_RES2 (0x1<<3) +#define MMCSD_CCC_BLKWT (0x1<<4) +#define MMCSD_CCC_ERASE (0x1<<5) +#define MMCSD_CCC_WRPT (0x1<<6) +#define MMCSD_CCC_LOCK (0x1<<7) +#define MMCSD_CCC_APP (0x1<<8) +#define MMCSD_CCC9 (0x1<<9) +#define MMCSD_CCC10 (0x1<<10) + + +/*--------------------------------------------------------------------------*/ +/* DEFINE CARD DOMAIN */ +/*--------------------------------------------------------------------------*/ +#define MMCSD_CAPA4M 4 /* 4 MByte */ +#define MMCSD_CAPA8M 8 /* 8 MByte */ +#define MMCSD_CAPA16M 16 /* 16 MByte */ +#define MMCSD_CAPA32M 32 /* 32 MByte */ +#define MMCSD_CAPA48M 48 /* 48 MByte */ +#define MMCSD_CAPA64M 64 /* 64 MByte */ +#define MMCSD_CAPA128M 128 /* 128 MByte */ + + +/*--------------------------------------------------------------------------*/ +/* DEFINE RESPONSES */ +/*--------------------------------------------------------------------------*/ +#define MMCSD_RES1LEN 0x0030 /* (MMC)RESPONSE1BIT LENGTH */ +#define MMCSD_RES2LEN 0x0088 /* (MMC)RESPONSE2BIT LENGTH */ +#define MMCSD_RES3LEN 0x0030 /* (MMC)RESPONSE3BIT LENGTH */ +#define MMCSD_RES4LEN 0x0030 /* (MMC)RESPONSE4BIT LENGTH */ +#define MMCSD_RES5LEN 0x0030 /* (MMC)RESPONSE5BIT LENGTH */ + + +/*--------------------------------------------------------------------------*/ +/* DEFINE WAIT CLOCK */ +/*--------------------------------------------------------------------------*/ +#define MMCSD_WAIT_UNIT 8 +#define MMCSD_NCS_MIN 0*WAIT_UNIT +#define MMCSD_NCS_MAX 1*WAIT_UNIT +#define MMCSD_NCR_MIN 1*WAIT_UNIT +#define MMCSD_NCR_MAX 8*WAIT_UNIT +#define MMCSD_NRC_MIN 1*WAIT_UNIT +#define MMCSD_NRC_MAX 1*WAIT_UNIT +#define MMCSD_NAC_MIN 1*WAIT_UNIT +#define MMCSD_NAC_MAX 16*WAIT_UNIT +#define MMCSD_NWR_MIN 1*WAIT_UNIT +#define MMCSD_NWR_MAX 1*WAIT_UNIT +#define MMCSD_BUSY_WAIT 0xFFFFFFFF/* = 65535(decimal) */ + +#define MMCSD_CMD_BITLEN 48 /* BIT LENGTH OF CMD */ +#define MMCSD_CSD_BYTELEN 16 /* CSD BYTE LENGTH */ +#define MMCSD_CSD_BITLEN 128 /* CSD BIT LENGTH */ +#define MMCSD_CID_BITLEN 128 /* CID BIT LENGTH */ + +#define MMCSD_CSD_CLOCK (CSD_BYTELEN+CRC16LEN)*8 +#define MMCSD_READ_CLOCK (MMCSD_BLOCKLEN+CRC16LEN)*8 +#define MMCSD_WRITE_CLOCK MMCSD_BLOCKLEN*8 +#define MMCSD_CRC_CLOCK CRC16LEN*8 +#define MMCSD_DATARES_CLOCK 4 + + +#define MMCSD_WAIT_CSDCLOCK (NCR_MAX+SPI_RESR2LEN+NAC_MAX+CSD_LEN) +#define MMCSD_WAIT_CIDCLOCK (NCR_MAX+SPI_RESR2LEN+NAC_MAX+CID_LEN) + +/*---------------------Register Define------------------------------------------*/ +#ifdef CONFIG_ARCH_MX1ADS //for MX1 +#define MMCSDR_BASE 0xF0214000 +#endif +#ifdef CONFIG_ARCH_MX2ADS +#define MMCSDR_BASE IO_ADDRESS(0x10013000) +#define MMCSDR_BASE_2 IO_ADDRESS(0x10014000)//for SD2 +#endif + +#define MMCSDR_STR_STP_CLK (MMCSDR_BASE) +#define MMCSDR_STATUS (MMCSDR_BASE+0x4) +#define MMCSDR_CLK_RATE (MMCSDR_BASE+0x8) +#define MMCSDR_CMD_DAT_CONT (MMCSDR_BASE+0xC) +#define MMCSDR_RES_TO (MMCSDR_BASE+0x10) +#define MMCSDR_READ_TO (MMCSDR_BASE+0x14) +#define MMCSDR_BLK_LEN (MMCSDR_BASE+0x18) +#define MMCSDR_NOB (MMCSDR_BASE+0x1C) +#define MMCSDR_REV_NO (MMCSDR_BASE+0x20) +#define MMCSDR_INT_MASK (MMCSDR_BASE+0x24) +#define MMCSDR_CMD (MMCSDR_BASE+0x28) +#define MMCSDR_ARGUMENTH (MMCSDR_BASE+0x2C) +#define MMCSDR_ARGUMENTL (MMCSDR_BASE+0x30) +#define MMCSDR_RES_FIFO (MMCSDR_BASE+0x34) +#define MMCSDR_BUFFER_ACCESS (MMCSDR_BASE+0x38) +#define MMCSDR_BUF_PART_FULL (MMCSDR_BASE+0x3c) + + +#define mmcsdr_str_stp_clk (*((volatile unsigned long *)(MMCSDR_STR_STP_CLK))) +#define mmcsdr_status (*((volatile unsigned long *)(MMCSDR_STATUS))) +#define mmcsdr_clk_rate (*((volatile unsigned long *)(MMCSDR_CLK_RATE))) +#define mmcsdr_cmd_dat_cont (*((volatile unsigned long *)(MMCSDR_CMD_DAT_CONT))) +#define mmcsdr_res_to (*((volatile unsigned long *)(MMCSDR_RES_TO))) +#define mmcsdr_read_to (*((volatile unsigned long *)(MMCSDR_READ_TO))) +#define mmcsdr_blk_len (*((volatile unsigned long *)(MMCSDR_BLK_LEN))) +#define mmcsdr_nob (*((volatile unsigned long *)(MMCSDR_NOB))) +#define mmcsdr_rev_no (*((volatile unsigned long *)(MMCSDR_REV_NO))) +#define mmcsdr_int_mask (*((volatile unsigned long *)(MMCSDR_INT_MASK))) +#define mmcsdr_cmd (*((volatile unsigned long *)(MMCSDR_CMD))) +#define mmcsdr_argumenth (*((volatile unsigned long *)(MMCSDR_ARGUMENTH))) +#define mmcsdr_argumentl (*((volatile unsigned long *)(MMCSDR_ARGUMENTL))) +#define mmcsdr_res_fifo (*((volatile unsigned long *)(MMCSDR_RES_FIFO))) +#define mmcsdr_buffer_access (*((volatile unsigned long *)(MMCSDR_BUFFER_ACCESS))) + +#ifdef CONFIG_ARCH_MX2ADS + +#define MMCSDR_STR_STP_CLK_2 (MMCSDR_BASE_2) +#define MMCSDR_STATUS_2 (MMCSDR_BASE_2+0x4) +#define MMCSDR_CLK_RATE_2 (MMCSDR_BASE_2+0x8) +#define MMCSDR_CMD_DAT_CONT_2 (MMCSDR_BASE_2+0xC) +#define MMCSDR_RES_TO_2 (MMCSDR_BASE_2+0x10) +#define MMCSDR_READ_TO_2 (MMCSDR_BASE_2+0x14) +#define MMCSDR_BLK_LEN_2 (MMCSDR_BASE_2+0x18) +#define MMCSDR_NOB_2 (MMCSDR_BASE_2+0x1C) +#define MMCSDR_REV_NO_2 (MMCSDR_BASE_2+0x20) +#define MMCSDR_INT_MASK_2 (MMCSDR_BASE_2+0x24) +#define MMCSDR_CMD_2 (MMCSDR_BASE_2+0x28) +#define MMCSDR_ARGUMENTH_2 (MMCSDR_BASE_2+0x2C) +#define MMCSDR_ARGUMENTL_2 (MMCSDR_BASE_2+0x30) +#define MMCSDR_RES_FIFO_2 (MMCSDR_BASE_2+0x34) +#define MMCSDR_BUFFER_ACCESS_2 (MMCSDR_BASE_2+0x38) + +#define mmcsdr_str_stp_clk_2 (*((volatile unsigned long *)(MMCSDR_STR_STP_CLK_2))) +#define mmcsdr_status_2 (*((volatile unsigned long *)(MMCSDR_STATUS_2))) +#define mmcsdr_clk_rate_2 (*((volatile unsigned long *)(MMCSDR_CLK_RATE_2))) +#define mmcsdr_cmd_dat_cont_2 (*((volatile unsigned long *)(MMCSDR_CMD_DAT_CONT_2))) +#define mmcsdr_res_to_2 (*((volatile unsigned long *)(MMCSDR_RES_TO_2))) +#define mmcsdr_read_to_2 (*((volatile unsigned long *)(MMCSDR_READ_TO_2))) +#define mmcsdr_blk_len_2 (*((volatile unsigned long *)(MMCSDR_BLK_LEN_2))) +#define mmcsdr_nob_2 (*((volatile unsigned long *)(MMCSDR_NOB_2))) +#define mmcsdr_rev_no_2 (*((volatile unsigned long *)(MMCSDR_REV_NO_2))) +#define mmcsdr_int_mask_2 (*((volatile unsigned long *)(MMCSDR_INT_MASK_2))) +#define mmcsdr_cmd_2 (*((volatile unsigned long *)(MMCSDR_CMD_2))) +#define mmcsdr_argumenth_2 (*((volatile unsigned long *)(MMCSDR_ARGUMENTH_2))) +#define mmcsdr_argumentl_2 (*((volatile unsigned long *)(MMCSDR_ARGUMENTL_2))) +#define mmcsdr_res_fifo_2 (*((volatile unsigned long *)(MMCSDR_RES_FIFO_2))) +#define mmcsdr_buffer_access_2 (*((volatile unsigned long *)(MMCSDR_BUFFER_ACCESS_2))) +#endif + +#define MMCSDB_R1 0x01 +#define MMCSDB_R2 0x02 +#define MMCSDB_R3 0x03 +#define MMCSDB_R5 0x05 +#define MMCSDB_DATEN 0x08 +#define MMCSDB_WRRD 0x10 +#define MMCSDB_STRBLK 0x20 +#define MMCSDB_BSY 0x40 +#define MMCSDB_INIT 0x80 +#define MMCSD_BUS_4BIT 0x200 + +/*-------------------- Mask Definitions --------------------------------------*/ +#define MMCSD_CLOCK_MASK 0x0000003 + +/*--------------------Finish wait condition--------------------------------------*/ +#define MMCSD_CMD_DONE 0x01 +#define MMCSD_DATA_TRANS_DONE 0x02 + +/*--------------------------------------------------------------------------*/ +/* ILLEGAL ERRORS THAT SOFTWARE CHECKS */ +/*--------------------------------------------------------------------------*/ + +#define MMCSD_CSD_MISS 0x1000/* ABNORMAL CSD */ +#define MMCSD_CID_MISS 0x2000/* ABNORMAL CID */ +#define MMCSD_MBR_ERROR 0x3000/* ABNORMAL MBR DATA */ +#define MMCSD_BPB_ERROR 0x4000/* ABNORMAL BPB DATA */ +#define MMCSD_NO_CARD 0x5000/* CANNOT IDENTIFY CARD */ +#define MMCSD_NOT_EXIST_AREA 0x6000/* ACCESS TO NON-EXIST DOMAIN */ +#define MMCSD_ILLEGAL_STATE 0x7000 + +#define MMCSD_ILLEGAL_ERROR_MASK 0xF000 + +#define MMCSD_STATUS_NOERROR 0xFDFF0000 + +#define MMCSD_READ_TIMEOUT 0x1 //fix +#define MMCSD_CMD_TIMEOUT 0x2 //fix with MMC status register. CMD error +#define MMCSD_WRITE_CRC 0x4 //fix +#define MMCSD_READ_CRC 0x8 //fix +#define MMCSD_HARDWARE_REV 0x10 +#define MMCSD_RESP_CRC_ERR 0x20 //fix with MMC status register. CMD error +#define MMCSD_CARD_BUSY 0x200 //only use in CMD1 +#define MMCSD_END_CMD_RESP 0x2000 + +#define MMCSD_STATUS_ERR (MMCSD_READ_TIMEOUT|MMCSD_CMD_TIMEOUT|MMCSD_WRITE_CRC) +//#define MMCSD_STATUS_ERR (MMCSD_READ_TIMEOUT|MMCSD_CMD_TIMEOUT|MMCSD_WRITE_CRC|MMCSD_RESP_CRC_ERR) + +#define MMCSD_STATUS u32 + + +#define MMCSD_ADP_REPEATNUM 1500 /* Define retry times*/ +#define MMCSD_MMC_CARD_VOLTAGE 0x00ff8000 +#define MMCSD_CARD_VOLTAGE 0x00ff8000 +#define MMCSD_CARD_SET_VOLTAGE 0x00008000 + + + +/*--------------------------------------------------------------------------*/ +/* Pin Configuration */ +/*--------------------------------------------------------------------------*/ +#ifndef CONFIG_ARCH_MX2ADS +#define DBMX1_GIUS_B 0xf021c120 +#define DBMX1_GPR_B 0xf021c138 +#define DBMX1_PUEN_B 0xf021c140 +#define DBMX1_DDIR_B 0xf021c100 +#define DBMX1_OCR1_B 0xf021c104 +#define DBMX1_DR_B 0xf021c11c +#define DBMX1_IMR_B 0xf021c130 +#define DBMX1_ICR2_B 0xf021c12c +#define DBMX1_ISR_B 0xf021c134 + +#define AIPI2_BASE_ADDR 0xF0210000 +#define AIPI2_PSR0 AIPI2_BASE_ADDR // ; Peripheral Size Reg 0 +#define AIPI2_PSR1 (AIPI2_BASE_ADDR+0x04) // ; Peripheral Size Reg 1 +#define AIPI2_PAR (AIPI2_BASE_ADDR+0x08) // ; Peripheral Access Reg + +#define CRM_BASE_ADDR 0xF021B000 +#define CRM_CSCR CRM_BASE_ADDR // ; Clock Source Control Reg +#define CRM_MPCTL0 (CRM_BASE_ADDR+0x04) // ; MCU PLL Control Reg +#define CRM_MPCTL1 (CRM_BASE_ADDR+0x08) // ; MCU PLL & System Clk Ctl Reg +#define CRM_UPCTL0 (CRM_BASE_ADDR+0x0C) // ; USB PLL Control Reg 0 +#define CRM_UPCTL1 (CRM_BASE_ADDR+0x10) // ; USB PLL Control Reg 1 +#define CRM_PCDR (CRM_BASE_ADDR+0x20) // ; Perpheral Clock Divider Reg + +#define CRM_RSR (CRM_BASE_ADDR+0x800) // ; Reset Source Reg +#define CRM_SIDR (CRM_BASE_ADDR+0x804) // ; Silicon ID Reg +#define CRM_FMCR (CRM_BASE_ADDR+0x808) // ; Functional Muxing Control Reg +#define CRM_GPCR (CRM_BASE_ADDR+0x80C) // ; Global Control Reg + +#define PLL_BASE 0xF021B000 + +/* Reset Module*/ +#define PLL_CSCR (PLL_BASE+0x00) //Clock Source Control Register +#define PLL_PCDR (PLL_BASE+0x20) //Peripherial Clock Divider Register +/* PLL & Clock Controller */ +#define PLL_MCTL0 (PLL_BASE+0x04) //MCU PLL Control Register 0 +#define PLL_MCTL1 (PLL_BASE+0x08) //MCU PLL Control Register 1 +#define PLL_UPCTL0 (PLL_BASE+0x0C) //USB PLL Control Register 0 +#define PLL_UPCTL1 (PLL_BASE+0x10) //USB PLL Control Register 1 +/* System Control */ +#define PLL_RSR (PLL_BASE+0x800) //Reset Source Register +#define PLL_SIDR (PLL_BASE+0x804) //Silicon ID Register +#define PLL_FMCR (PLL_BASE+0x808) //Function Muxing Control Register +#define PLL_GPCR (PLL_BASE+0x80C) //Global Peripherial Control Regiser +#else //for MX21 + +#endif + + + +#endif diff -Nru src.org/drivers/mx1mmc/mmc_drv.c src/drivers/mx1mmc/mmc_drv.c --- src.org/drivers/mx1mmc/mmc_drv.c Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/mmc_drv.c Fri Sep 30 19:38:40 2005 @@ -0,0 +1,773 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2002 Motorola Semiconductors HK Ltd + * + */ + + +/****************************************************************************** + * + * Copyright (C) 2001, Motorola All Rights Reserved + * + * File Name: mmcsd.c + * + * Progammers: Yiwei Zhao + * + * Date of Creations: 30 DEC,2001 + * + * Synopsis: + * + * Modification History: + * 30 DEC, 2001 + * + *****************************************************************************/ + + +#include "dbmx1_type.h" +#include "mmc_def.h" +#include "mmc_main.h" + +/* Functions List: + * + */ +//Karen add for write protect +#define _reg_I2C_IADR (*((volatile unsigned long*)(0xf0217000))) +#define _reg_I2C_IFDR (*((volatile unsigned long*)(0xf0217004))) +#define _reg_I2C_I2CR (*((volatile unsigned long*)(0xf0217008))) +#define _reg_I2C_I2SR (*((volatile unsigned long*)(0xf021700c))) +#define _reg_I2C_I2DR (*((volatile unsigned long*)(0xf0217010))) + + +#define _reg_PTA_GIUS (*((volatile unsigned long*)(0xf021C020))) +#define _reg_PTA_PUEN (*((volatile unsigned long*)(0xf021C040))) + +unsigned long* pI2CReadData; +unsigned short nI2CReadData;//number of data +unsigned short nI2CData; // index of data +unsigned long dI2CReadData[2]; +unsigned char bTransferDone; +unsigned char bTransferCurMode; +unsigned char gSDWriteProtect; + +#define KAREN_DEBUG + +/* + * Implementation of the MMCSD Driver. + */ +/****************************************************************************** + * Function Name: _MMCSD_InitCard + * + * Input: None. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * this routine will initialize the cards. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +MMCSD_STATUS _MMCSD_InitSDHC(int port) +{ + MMCSD_STATUS ret; + +#ifdef CONFIG_ARCH_MX2ADS + if(port == 0)//sdhc1 + { + //set i/o driving strength + _reg_SYS_DSCR1 &= ~0x07; + // _reg_SYS_DSCR1 |= 0x01;//4mA + _reg_SYS_DSCR1 |= 0x03;//6mA + + } + else if(port == 1) + { + _reg_SYS_DSCR1 &= ~0x00380000; + // _reg_SYS_DSCR1 |= 0x00080000;//4mA + _reg_SYS_DSCR1 |= 0x00180000;//6mA + } +#else + port = 0; +#endif + //check hardware revision + ret=_MMCSD_ChectHardwareRevision(port); + if(ret) + return ret; + //softreset + ret=_MMCSD_SoftReset(port); + if(ret) + return ret; + _MMCSD_SetClk(MMCSD_LOW_SPEED,port); + _MMCSD_ReadTimeOut(0x2DB4,port); + + ret=_MMCSD_ChectHardwareRevision(0); + if(ret) + return ret; + ret=_MMCSD_SoftReset(0); + if(ret) + return ret; + + _MMCSD_SetClk(MMCSD_LOW_SPEED,0); + + _MMCSD_ReadTimeOut(0x2DB4,0); + return 0; + +} + +MMCSD_STATUS _MMCSD_InitMMC(int port) +{ + u16 i, count; + MMCSD_STATUS ret; + u8 Cid_buff[20]; + u16 card_type = 0xFFFF; + count = 0; + ret = 0; + + //TRACE("Card Identify\n"); + /*------------------------------------------------------------------*/ + /* CMD0 CALL PROCEDURE (PLACES CARDS IN IDLE STATE) */ + /*------------------------------------------------------------------*/ + + ret =_MMCSD_GoIdleState(port); + if(ret != 0 ) + { /*--------- WHEN NO ERROR OCCURS (= FINISH INIT)*/ + FAILED("Place Cards into Idle State Failed(%ld)",(unsigned long)ret); + return ret; + } + + /*------------------------------------------------------------------*/ + /* CMD1 */ + /*------------------------------------------------------------------*/ + i = MMCSD_ADP_REPEATNUM; + + while (i--) + { + ret = _MMCSD_SendOpCond(MMCSD_MMC_CARD_VOLTAGE,port); + if (ret == 0) + break; // card detected + + if (ret != MMCSD_CARD_BUSY) + { + //FAILED("Command SendOpCond Failed"); + return ret; //CMD send ERROR + } + } + /*------------------------------------------------------------------*/ + /* Register CARDS */ + /*------------------------------------------------------------------*/ + + /* + TRACE("Set Op Condition.."); + ret = _MMCSD_Set_SendOpCond(MMCSD_MMC_CARD_VOLTAGE, + MMCSD_CARD_SET_VOLTAGE); + if(ret) + { + FAILED("MMCSD_SendOpCond(SET_VOLTAGE) error with 0x%x",ret); + return ret; + } + */ + + /* + * Aleph: only one card supported. + */ + ret = _MMCSD_AllSendCID(Cid_buff,port); //CMD2 + if (ret & MMCSD_CMD_TIMEOUT) + { + FAILED("_MMCSD_AllSendCID failed with 0x%lx",(unsigned long)ret); + g_mmcsd_devices[port].card_state = MMCSD_NOTREADY; + return ret; + } + + ret = _MMCSD_SetRelativeAddr(&g_mmcsd_devices[port].card_rca, port); //CMD3 + + g_mmcsd_devices[port].card_state = MMCSD_STANDBY; + count++; + + /*----------------------------------------------------------------------*/ + /* CHECK IF EFFECTIVE CARDS EXIST */ + /*----------------------------------------------------------------------*/ + if ( count ) + { /*------------------------- IF THERE IS AN EFFECTIVE CARD */ + g_mmcsd_num = count; /* ACQUIRE THE NUMBER */ + //TRACE("Finish Init Card. %d Cards have beed detected\n",count); + return MMCSD_OK; + } + else + { /*--------------------- WHEN NO EFFECTIVE CARD IS IDENTIFIED */ + INFO("No Card is detected\n"); + return( MMCSD_NO_CARD ); + } + return( ret ); +} + +/****************************************************************************** + * Function Name: _MMCSD_InitCard + * + * Input: + * device: pointer to MMCSD_Dev structure. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * Check and aqquire CSD/CID register data + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +MMCSD_STATUS _MMCSD_GetInfo(MMCSD_Dev *device) +{ + MMCSD_STATUS ret; + u8 Csd_buff[20]; /* BUFFER FOR RECEIVING CSD */ + u8 Cid_buff[20]; /* BUFFER FOR RECEIVING CID */ + u32 port; + TRACE("Get Card Info\n"); + ret = 0; + port = device->port; + _MMCSD_SetBlockLenReg(0x10,port); // Why???? + + ret = _MMCSD_SendCSD( device->card_rca,Csd_buff,port); //CMD9 + if (ret) + { + FAILED("_MMCSD_SendCSD() error with 0x%lx",(unsigned long)ret); + return ret; + } + else + { + ret = _MMCSD_CSDCheck(Csd_buff); + if ( ret ) + { + FAILED("_MMCSD_CSDCheck error, ret=0x%lx",ret); + return ret; + } + else + { + _MMCSD_SetCSD(device,Csd_buff); + } + } + + ret = _MMCSD_SendCID( device->card_rca,Cid_buff,port); //CMD10 + if ( ret ) + { + FAILED("_MMCSD_SendCID() error with 0x%lx",(unsigned long)ret); + device->card_state = MMCSD_NOTREADY; + } + else + { + ret = _MMCSD_CIDCheck(Cid_buff); + if ( ret ) + { + FAILED("_MMCSD_CIDCheck() error with 0x%lx",ret); + return ret; + } + else + { + _MMCSD_SetCID(device, Cid_buff); + } + } + return( ret ); +} + +/****************************************************************************** + * Function Name: _MMCSD_SetSectLen + * + * Input: None. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + * Why??? this function must be here, otherwise CRC-WRITE-ERROR while polling write. + *****************************************************************************/ + +MMCSD_STATUS _MMCSD_SetSectLen(MMCSD_Dev *device) +{ + + u8 type; + MMCSD_STATUS ret; + /*----------------------------------------------------------------------*/ + /* INITIALIZE LOCAL VARIABLES */ + /*----------------------------------------------------------------------*/ + type = 0; /* CMD TYPE = NO DATA TRANSFER */ + ret = 0; /* SEND/RECEIVE ERROR */ + + /*--------------------------------------------------------------*/ + /* CARD SELECT */ + /*--------------------------------------------------------------*/ + + ret = _MMCSD_SelectDeselectCard(device->card_rca,device->port); + if ( ret ) + { + device->card_state = MMCSD_NOTREADY; + return ret; + } + /* + ret = _MMCSD_SetBlockLen(MMCSD_MINIMUM_BLK_SIZE,1); // + if ( ret ) + { + device->card_state = MMCSD_NOTREADY; + return ret; + } + device->blksize = MMCSD_MINIMUM_BLK_SIZE; + */ + ret = _MMCSD_SelectDeselectCard(0,device->port); + if ( ret ) + { + device->card_state = MMCSD_NOTREADY; + return ret; + } + device->card_state = MMCSD_STANDBY; + + return( ret ); +} +/****************************************************************************** + * Function Name: _MMCSD_GetStatus + * + * Input: None. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +u32 _MMCSD_GetStatus(MMCSD_Dev *device) +{ + u32 state; + MMCSD_STATUS ret=_MMCSD_SendStatus(device->card_rca,&state,device->port); + + ret&=MMCSD_STATUS_NOERROR|0xFFFF; + + if ( ret ) + { + device->card_state = MMCSD_NOTREADY; + } + else + { + device->card_state = MMCSD_STANDBY; + } + return( ret ); +} + + +/****************************************************************************** + * Function Name: _MMCSD_SetCSD + * + * Input: None. + * + * Value Returned: + * + * Description: + * + * Get CSD Info + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +void _MMCSD_SetCSD(MMCSD_Dev *device,u8 * Csd_buff) +{ + u32 size,t1,t2; + u32 read_bl_len; /* read data block length */ + u32 c_size; /* device size */ + u32 mult,blocknr,block_len; + u32 c_size_mult; + u8 write_blk_len; + u8 erase_sector_size; /* erase sector size */ + u8 wp_grp_size; + + read_bl_len=( Csd_buff[5] & 0x0F ); + //TRACE("Read Block Length [5] 0x%x",read_bl_len); + + device->ccc = (Csd_buff[5]&0xF0)>>4; + device->ccc |= Csd_buff[4]<<4; + + c_size=0; + t1=Csd_buff[6]&0x3; + t1=t1<<10; + + t2=Csd_buff[7]; + t2=t2<<2; + t2=t1|t2; + + c_size=(t2|((Csd_buff[8]&0xC0)>>6)); + + //erase_sector_size=( ( Csd_buff[10] & 0x7C ) >> 2 ); + erase_sector_size=0; + erase_sector_size=((Csd_buff[10]&0x3F)<<1); + erase_sector_size= erase_sector_size|((Csd_buff[11]&0x80)>>7); + erase_sector_size++; + + wp_grp_size = 0; + wp_grp_size = (Csd_buff[11]&0x3F)+1; + + + write_blk_len = 0; + write_blk_len = (Csd_buff[12]&0x03)<<2; + write_blk_len = write_blk_len|((Csd_buff[13]&0xc0)>>6); + + c_size_mult=( ( ( Csd_buff[9] & 0x03 ) << 1 )| + ( ( Csd_buff[10] & 0x80 ) >> 7 ) ); + + mult=1<<(c_size_mult+2); + blocknr=(c_size+1)*mult; + block_len=1<dev_size=size; + device->sect_num=size/MMCSD_MINIMUM_BLK_SIZE; + device->blksize = MMCSD_MINIMUM_BLK_SIZE; + device->blksize_bit = 9; + + device->phy_blksize = 1<phy_sectorsize = (device->phy_blksize)*erase_sector_size; + device->wp_grp_size = (device->phy_sectorsize)*wp_grp_size; + + INFO("write block size is %d",device->phy_blksize); + INFO("Erase sector size is %ld",(long int)(device->phy_sectorsize)); + INFO("Card Size is %ld bytes, sect_num (for FAT file system) is %ld\n", + (long int)size,size/MMCSD_MINIMUM_BLK_SIZE); + INFO("Supported Card Command Class is 0x%0X\n",device->ccc); + //INFO("Wirte Protected group size [11] = 0x%x",wp_grp_size); + +} +/****************************************************************************** + * Function Name: _MMCSD_SetCID + * + * Input: None. + * + * Value Returned: + * + * Description: + * + * Set CID + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +void _MMCSD_SetCID(MMCSD_Dev *device,u8* Cid_buff) +{ + + int j; + for(j=0;j<16;j++) + device->CID[j]=Cid_buff[j]; +} + + +/****************************************************************************** + * Function Name: _MMCSD_CSDCheck + * + * Input: None. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * Check CSD register + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +/**************************************************************************** + CSD Register + ----------------------------------------------------------------------------- + Name | Width| CSD_Slice| pCsdbuff (BYTE) + ----------------------------------------------------------------------------- + CSD struction 2 127:126 + System spec. version 4 125:122 0 + reserved 2 121:120 + ----------------------------------------------------------------------------- + data read access time 1 8 119:112 1 + ----------------------------------------------------------------------------- + data read access time 2 8 111:104 2 + ----------------------------------------------------------------------------- + Max data transfer rate 8 103:96 3 + ----------------------------------------------------------------------------- + card command classes 12 95:84 4 + max read data block length 4 83:80 5 + ------------------------------------------------------------------------------ + partial blocks for read length 1 79:79 + wirte block misalignment 1 78:78 + read block misalignment 1 77:77 + DSR implemented 1 76:76 + reserved 2 75:74 + device size 12 73:62 6-7 + max read current 3 61:69 + max read current 3 58-56 8 + ------------------------------------------------------------------------------ + max write current 3 55-53 + max write current 3 52-50 + device size multiplier 3 49-47 9 + erase sector size 5 46-42 + erase group size 5 41-37 10 + write protect group size 5 36-32 11 + ------------------------------------------------------------------------------ + write protect group enable 1 31:31 + manufactuter default ECC 2 30:29 + write speed factor 3 28:26 + max. write data block length 4 25:22 12 + partial blocks for write allowed 1 21:21 + reserved 5 20:16 13 + ------------------------------------------------------------------------------ + File format group 1 15:15 + copy flag 1 14:14 + permanent write protection 1 13:13 + temporary write protection 1 12:12 + file format 2 11:10 + ECC code 2 9:8 14 + -------------------------------------------------------------------------------- + CRC 7 7:1 + Not used always '1' 1 0:0 15 + ------------------------------------------------------------------------------- + *********************************************************************************/ + +MMCSD_STATUS _MMCSD_CSDCheck(u8 *csdbuff ) +{ + u8 temp; + temp = 0; + + /*----------------------------------------------------------------------*/ + /* CHECK FROM THE BEGINNING */ + /*----------------------------------------------------------------------*/ + /*---------------------- CSD_STRUCTURE ---------------------------------*/ + temp = ( ( csdbuff[0] & 0xC0 ) >> 6 ); + if ( ( temp != 0 )&&( temp != 1 ) ) + { +#ifdef KAREN_DEBUG + // printk("CSD_STRUCTURE = %x \n",temp); +#endif + //Karen + //return( MMCSD_CSD_MISS );//Karen modified + //end Karen + } + /*------------------------- MMC_PORT -----------------------------------*/ + temp = ( ( csdbuff[0] & 0x3C ) >> 2 ); + if ( ( temp != 0 )&&( temp != 1 )&&( temp != 2 ) ) + { +#ifdef KAREN_DEBUG + // printk("MMC_PORT = %x \n",temp); +#endif + //Karen + // return( MMCSD_CSD_MISS ); + //end Karen + } + /*------------------------- TACC ---------------------------------------*/ + temp = ( csdbuff[1] & 0x80 ); + if ( temp != 0 ) + { +#ifdef KAREN_DEBUG + printk("TACC = %x \n",temp); +#endif + //Karen + // return( MMCSD_CSD_MISS ); + //end Karen + } + /*------------------------- NSAC ---------------------------------------*/ + /*---------------------- TRAN_SPEED ------------------------------------*/ + temp = ( csdbuff[3] & 0x80 ); + if ( temp != 0 ) + { +#ifdef KAREN_DEBUG + printk("TRAN_SPEED = %x \n",temp); +#endif + //Karen + // return( MMCSD_CSD_MISS ); + //end Karen + } + /*-------------------------- CCC ---------------------------------------*/ + + // TRACE("CCC: ----- 0x%0X",device->ccc); + /*---------------------- READ_BL_LEN -----------------------------------*/ + temp = ( csdbuff[5] & 0x0F ); + if ( temp > 0x0B ) + { +#ifdef KAREN_DEBUG + printk("READ_BL_LEN = %x \n",temp); +#endif + //Karen + // return( MMCSD_CSD_MISS ); + // end Karen + } + /*-------------------- READ_BL_PARTIAL ---------------------------------*/ + /*------------------ WRITE_BLK_MISALIGN --------------------------------*/ + /*------------------- READ_BLK_MISALIGN --------------------------------*/ + /*-------------------------- DSR_IMP -----------------------------------*/ + /*--------------------------- C_SIZE -----------------------------------*/ + /*------------------- VDD_R_CURR_MIN,VDD_W_CURR_MIN --------------------*/ + /*------------------- VDD_R_CURR_MAX,VDD_W_CURR_MAX --------------------*/ + /*------------------------- C_SIZE_MULT --------------------------------*/ + /*------------------------- SECTOR_SIZE --------------------------------*/ + /*------------------------- ERASE_GRP_SIZE -----------------------------*/ + /*-------------------------- WP_GRP_SIZE -------------------------------*/ + /*------------------------ WP_GRP_ENABLE -------------------------------*/ + /*------------------------- DEFAULT_ECC --------------------------------*/ + /*-------------------------- R2W_FACTOR --------------------------------*/ + temp = (( csdbuff[12] & 0x1C ) >> 2 ); + if ( temp > 5 ) + { +#ifdef KAREN_DEBUG + printk("R2W_FACTOR = %x \n",temp); +#endif + //Karen + // return( MMCSD_CSD_MISS ); + //end Karen + } + /*------------------------- WRITE_BL_LEN -------------------------------*/ + /*------------------------ WRITE_BL_PARTIAL ----------------------------*/ + /*---------------------------- COPY ------------------------------------*/ + /*----------------------- PERM_WRITE_PROTECT ---------------------------*/ + /*------------------------ TMP_WRITE_PROTECT ---------------------------*/ + /*----------------------------- ECC ------------------------------------*/ + temp = ( csdbuff[14] & 0x03 ); + if ( temp > 1 ) + { +#ifdef KAREN_DEBUG + printk("ECC = %x \n",temp); +#endif + //Karen + // return( MMCSD_CSD_MISS ); + //end Karen + } + /*----------------------------- CRC ------------------------------------*/ + temp = ( csdbuff[15] & 0x01 ); + if ( temp != 1 ) + { + // PLAM + return((MMCSD_STATUS)0); + //return( MMCSD_CSD_MISS ); + // end PLAM + } + else{/* IF NO ERROR BEFORE HERE, DO A NORMAL RETURN */ + return( (MMCSD_STATUS)0 ); + } +} + +/****************************************************************************** + * Function Name: _MMCSD_CIDCheck + * + * Input: None. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * Check CID register + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +/***************************************************************************** + + CID Register:(Bit) 127 119 111 103 95 87 79 71 63 55 47 39 31 15 7 0 + ------------------------------------------------------------------------------------------ + CID Register |MID | OID | PNM | PSN |MDT| CRC| + ------------------------------------------------------------------------------------------ +pCidBuff :(BYTE) | 0 | 1 | 2 | 4 | 5 | 7 | 8 | 9 | 10| 11| 12|13| 14 | 15 | 16| + + + ******************************************************************************/ + +MMCSD_STATUS _MMCSD_CIDCheck( u8 *cidbuff ) +{ + /*----------------------------------------------------------------------*/ + /* TOTAL CHECK FROM THE BEGINNING */ + /*----------------------------------------------------------------------*/ + /*-------------------------- Manufacturer ID ---------------------------*/ + if (( cidbuff[0] == 0 )&&( cidbuff[1] == 0 )&&( cidbuff[2] == 0 )) + { + return( MMCSD_CID_MISS ); + } + /*----------------------- Card individual number -----------------------*/ + if (( cidbuff[3] == 0 )&&( cidbuff[4] == 0 )&&( cidbuff[5] == 0 )&& + ( cidbuff[6] == 0 )&&( cidbuff[7] == 0 )&&( cidbuff[8] == 0 )&& + ( cidbuff[9] == 0 )&&( cidbuff[10] == 0 )&&( cidbuff[11] == 0 )&& + ( cidbuff[12] == 0 )&&( cidbuff[13] == 0 )&&( cidbuff[14] == 0 )) + { + return( MMCSD_CID_MISS ); + } + /*----------------- CRC7 checksum + not used,always'1' -----------------*/ + if ( ( cidbuff[15] & 0x01 ) != 0x01 ) + { + // PLAM + return 0; + // return( MMCSD_CID_MISS ); + // end PLAM + } + return( 0 ); +} +/* + MMCSD_STATUS _MMCSD_SCRCheck(MMCSD_Dev *device) + { + MMCSD_Responses rp; + MMCSD_scr scr; + int ret; + + ret = _MMCSD_SendSCR(device->card_rca,&scr,device->port); + if(ret) + { + FAILED("SendSCR failed"); + return MMCSD_ERROR; + } + + if(scr.sd_bus_width&0x05) + { + INFO("can support both 1-bit & 4-bit \n"); + device->bit_width = 0; + return MMCSD_OK; + } + else if(scr.sd_bus_width&0x01) + { + INFO("can support only 1-bit \n"); + device->bit_width = 0; + return MMCSD_OK; + } + else if(scr.sd_bus_width&0x04) + { + INFO("can support only 4-bit \n"); + device->bit_width = 1; + return MMCSD_OK; + } + else + { + return MMCSD_ERROR; + } + + return MMCSD_OK; + } + */ diff -Nru src.org/drivers/mx1mmc/mmc_io.c src/drivers/mx1mmc/mmc_io.c --- src.org/drivers/mx1mmc/mmc_io.c Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/mmc_io.c Wed Sep 28 04:16:43 2005 @@ -0,0 +1,791 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2002 Motorola Semiconductors HK Ltd + * + */ + + +/****************************************************************************** + * + * Copyright (C) 2001, Motorola All Rights Reserved + * + * File Name: mmcsd.c + * + * Progammers: Yiwei Zhao + * + * Date of Creations: 30 DEC,2001 + * + * Synopsis: + * + * Modification History: + * 30 DEC, 2001 + * + *****************************************************************************/ + +/* Functions List: + * + * + * + */ + +/* + * Implementation of the MMCSD Driver. + */ +#include +#include "mmc_def.h" +#include "mmc_main.h" + + +static u32 cur_perclk2; +//pd25 +void _mmcsd_socket1_irq_set() +{ +#ifdef CONFIG_ARCH_MX1ADS + /* + *(u32 *)DBMX1_GIUS_B |= 0x00020000; + *(u32 *)DBMX1_DDIR_B &= ~0x00020000; + *(u32 *)DBMX1_IMR_B |= 0x00020000;//enable + *(u32 *)DBMX1_ICR2_B |= 0x0000000C;//negative level trigger + *(u32 *)DBMX1_PUEN_B &= ~0x00020000;//pull up enable interrupt + */ + // SD presence = PB20 + *(u32 *)DBMX1_GIUS_B |= 0x00100000; + *(u32 *)DBMX1_DDIR_B &= ~0x00100000; + *(u32 *)DBMX1_IMR_B |= 0x00100000;//enable + *(u32 *)DBMX1_ICR2_B |= 0x00000300;//negative level trigger + *(u32 *)DBMX1_PUEN_B &= ~0x00100000;//pull up enable interrupt +#endif +#ifdef CONFIG_ARCH_MX2ADS + _reg_GPIO_GIUS(GPIOD) |= 0x02000000; + _reg_GPIO_DDIR(GPIOD) &= ~0x02000000; + _reg_GPIO_IMR(GPIOD) |= 0x02000000;//enable + _reg_GPIO_ICR2(GPIOD) |= 0x000c0000;//negative level trigger + _reg_GPIO_PUEN(GPIOD) &= ~0x02000000; // pull up enable interrupt +#endif +} +void _mmcsd_socket1_clear_irq() +{ +#ifdef CONFIG_ARCH_MX1ADS + *(u32 *)DBMX1_ISR_B = 0x00100000; +#endif +#ifdef CONFIG_ARCH_MX2ADS + _reg_GPIO_ISR(GPIOD) = 0x02000000; +#endif +} +/****************************************************************************** + * Function Name: _MMCSD_CheckHardwareRevision + * + * Input: + * + * Value Returned: + * + * Description: + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ + +u32 _MMCSD_ChectHardwareRevision(int port) +{ + u32 HardwareID; + +#ifdef CONFIG_ARCH_MX1ADS + HardwareID = mmcsdr_rev_no; + TRACE("rev_no = %x \n",mmcsdr_rev_no); + if(HardwareID!=0x0390) + { + TRACE("HardwareID = 0x%x, return = %d", HardwareID,1); + return 1; //Hardware Revision Error; + } +#endif +#ifdef CONFIG_ARCH_MX2ADS + if(port == 0) + { + HardwareID = mmcsdr_rev_no; + } + else if(port == 1) + { + HardwareID = mmcsdr_rev_no_2; + } + if(HardwareID!=0x0400) + { + TRACE("HardwareID = 0x%x, return = %d", HardwareID,1); + return 1; //Hardware Revision Error; + } +#endif + return 0; +} + + +/****************************************************************************** + * Function Name: _MMCSD_SoftReset + * + * Input: + * + * Value Returned: + * + * Description: + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ +u32 _MMCSD_SoftReset(int port) +{ +#ifdef CONFIG_ARCH_MX1ADS + // System Reset + Start_Stop_Clk(0x8,0); + // System Reset, MMC core enable & Stop CLk + Start_Stop_Clk(0xD,0); + // MMC Core enable & Stop Clk + Start_Stop_Clk(0x5,0); + Start_Stop_Clk(0x5,0); + Start_Stop_Clk(0x5,0); + Start_Stop_Clk(0x5,0); + Start_Stop_Clk(0x5,0); + Start_Stop_Clk(0x5,0); + Start_Stop_Clk(0x5,0); + Start_Stop_Clk(0x5,0); + +#ifdef MMCSD_DMA_ENDIAN_ERR + // PLAM -- choose big endian FIFO mode + mmcsdr_str_stp_clk |= 0x00000020; + // end PLAM +#else + mmcsdr_str_stp_clk &= ~0x00000020; +#endif + //Set MMC Response Time-Out Register + mmcsdr_res_to=0xffff; + + //Set Block length register + mmcsdr_blk_len=MMCSD_MINIMUM_BLK_SIZE ;//2002/04/19 + + //Set MMC Number of Blocks Register + mmcsdr_nob=1;//2002/04/19 +#endif +#ifdef CONFIG_ARCH_MX2ADS + // System Reset + Start_Stop_Clk(0x8,port); + // System Reset, MMC core enable & Stop CLk + Start_Stop_Clk(0xD,port); + // MMC Core enable & Stop Clk + Start_Stop_Clk(0x5,port); + Start_Stop_Clk(0x5,port); + Start_Stop_Clk(0x5,port); + Start_Stop_Clk(0x5,port); + Start_Stop_Clk(0x5,port); + Start_Stop_Clk(0x5,port); + Start_Stop_Clk(0x5,port); + Start_Stop_Clk(0x5,port); + if(port == 0) + { + mmcsdr_str_stp_clk &= ~0x00000020; + //Set MMC Response Time-Out Register + mmcsdr_res_to=0xffff; + + //Set Block length register + mmcsdr_blk_len=MMCSD_MINIMUM_BLK_SIZE ; + + //Set MMC Number of Blocks Register + mmcsdr_nob=1; + } + else if(port == 1) + { + mmcsdr_str_stp_clk_2 &= ~0x00000020; + //Set MMC Response Time-Out Register + mmcsdr_res_to_2=0xffff; + + //Set Block length register + mmcsdr_blk_len_2=MMCSD_MINIMUM_BLK_SIZE ; + + //Set MMC Number of Blocks Register + mmcsdr_nob_2=1; + } +#endif + return 0; + +} + +void _MMCSD_ReadTimeOut(u32 arg,int port) +{ + arg = 0x2db4; +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + mmcsdr_read_to_2=0x2db4; + else + mmcsdr_read_to=0x2db4; +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_read_to=0x2db4; +#endif +} + +/****************************************************************************** + * Function Name: _MMCSD_SetCmd + * + * Input: + * + * Value Returned: + * + * Description: + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ +void _MMCSD_SetCmd(u8 cmd,u32 arg,u32 ctrl,int port) +{ +#ifdef MMCSD_CMD + TRACE(" ----------------------------------------"); + TRACE(" CMD%02d Arg: 0x%08lX Ctrl: 0x%04lX\n",cmd,arg,ctrl); +#endif +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + { + mmcsdr_cmd_2=cmd; + mmcsdr_argumenth_2=arg>>16; + mmcsdr_argumentl_2=arg&0xFFFF; + mmcsdr_cmd_dat_cont_2=ctrl; + } + else + { + mmcsdr_cmd=cmd; + mmcsdr_argumenth=arg>>16; + mmcsdr_argumentl=arg&0xFFFF; + mmcsdr_cmd_dat_cont=ctrl; + } +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_cmd=cmd; + mmcsdr_argumenth=arg>>16; + mmcsdr_argumentl=arg&0xFFFF; + mmcsdr_cmd_dat_cont=ctrl; +#endif +} + +/****************************************************************************** + * Function Name: _MMCSD_IsRun + * + * Input: + * + * Value Returned: + * + * Description: + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ +u32 _MMCSD_IsRun(int port) +{ +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + return (mmcsdr_status_2)&0x100; + else + return (mmcsdr_status)&0x100; +#endif +#ifdef CONFIG_ARCH_MX1ADS + return (mmcsdr_status)&0x100; +#endif +} + +/****************************************************************************** + * Function Name: _MMCSD_StartClk + * + * Input: + * + * Value Returned: + * + * Description: + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ +void _MMCSD_StartClk(int port) +{ + unsigned short count = 0; + do + { + if (count++ == 0) + { + // do this every 256 loops +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + mmcsdr_str_stp_clk_2 |= 0x06; + else + mmcsdr_str_stp_clk |= 0x06; +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_str_stp_clk |= 0x06; +#endif + } + } + while(!_MMCSD_IsRun(port)); +} + +/****************************************************************************** + * Function Name: _MMCSD_StopClk + * + * Input: + * + * Value Returned: + * + * Description: + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ +void _MMCSD_StopClk(int port) +{ + unsigned short count = 0; + do + { + if (count++ == 0) + { + // do this every 256 loops +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + mmcsdr_str_stp_clk_2 |= 0x05; + else + mmcsdr_str_stp_clk |= 0x05; +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_str_stp_clk |= 0x05; +#endif + } + }while(_MMCSD_IsRun(port)); +} + +/****************************************************************************** + * Function Name: _MMCSD_GetResponses + * + * Input: + * + * Value Returned: + * + * Description: + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ + +void _MMCSD_GetResponses(MMCSD_Responses *pRS, u8 rsType,int port) +{ + int i; + u16 rs; + u32 temp = 0; + + if(rsType==MMCSDB_R1) + { + pRS->status=0; +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + temp=(u32)mmcsdr_res_fifo_2; + else + temp=(u32)mmcsdr_res_fifo; +#endif +#ifdef CONFIG_ARCH_MX1ADS + temp=(u32)mmcsdr_res_fifo; +#endif + + rs=(u16)temp; + pRS->status|=((u32)rs&0x00FF)<<24; + +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + temp=(u32)mmcsdr_res_fifo_2; + else + temp=(u32)mmcsdr_res_fifo; +#endif +#ifdef CONFIG_ARCH_MX1ADS + temp=(u32)mmcsdr_res_fifo; +#endif + rs=(u16)temp; + pRS->status|=((u32)rs)<<8; + +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + temp=(u32)mmcsdr_res_fifo_2; + else + temp=(u32)mmcsdr_res_fifo; +#endif +#ifdef CONFIG_ARCH_MX1ADS + temp=(u32)mmcsdr_res_fifo; +#endif + rs=(u16)temp; + pRS->status|=(rs&0xFF00)>>8; + + } + else if(rsType==MMCSDB_R3) + { + pRS->OCR=0; + +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + temp=(u32)mmcsdr_res_fifo_2; + else + temp=(u32)mmcsdr_res_fifo; +#endif +#ifdef CONFIG_ARCH_MX1ADS + temp=(u32)mmcsdr_res_fifo; +#endif + rs=(u16)temp; + temp=rs&0x00FF; + pRS->OCR|=temp<<24; + +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + temp=(u32)mmcsdr_res_fifo_2; + else + temp=(u32)mmcsdr_res_fifo; +#endif +#ifdef CONFIG_ARCH_MX1ADS + temp=(u32)mmcsdr_res_fifo; +#endif + rs=(u16)temp; + pRS->OCR|=((u32)rs)<<8; + +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + temp=(u32)mmcsdr_res_fifo_2; + else + temp=(u32)mmcsdr_res_fifo; +#endif +#ifdef CONFIG_ARCH_MX1ADS + temp=(u32)mmcsdr_res_fifo; +#endif + rs=(u16)temp; + pRS->OCR|=(rs&0xFF00)>>8; + } + else + { + for(i=0;i<16;) + { +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + temp=(u32)mmcsdr_res_fifo_2; + else + temp=(u32)mmcsdr_res_fifo; +#endif +#ifdef CONFIG_ARCH_MX1ADS + temp=(u32)mmcsdr_res_fifo; +#endif + + rs=(u16)temp; + + pRS->CSD[i] = (rs&0xFF00)>>8; + i++; + pRS->CSD[i] = (rs&0x00FF); + i++; + } + } + +} + +/****************************************************************************** + * Function Name: _MMCSD_SetBlockLenReg + * + * Input: + * size: size of the block. + * + * Value Returned: + * + * + * Description: + * this routine sets the size of a block + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ +void _MMCSD_SetBlockLenReg(u16 size,u32 port) +{ +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + mmcsdr_blk_len_2=size; + else + mmcsdr_blk_len=size; +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_blk_len=size; +#endif +} + +/****************************************************************************** + * Function Name: _MMCSD_SetNumberOfBlockReg + * + * Input: + * + * num: Number of block + * + * Value Returned: + * + * + * Description: + * this routine sets number of the blocks. + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ + +void _MMCSD_SetNumberOfBlockReg(u16 num,u32 port) +{ +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + mmcsdr_nob_2=num; + else + mmcsdr_nob=num; +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_nob=num; +#endif +} + +/****************************************************************************** + * Function Name: _MMCSD_ClockSet + * + * Input: + * + * speed: if speed == oxff, set the highest speed. + * + * Value Returned: + * + * + * Description: + * this routine set clock rate. + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ + +void _MMCSD_ClockSet(u32 prescaler,u8 clk,int port) +{ + _MMCSD_StopClk(port); + +#ifdef CONFIG_ARCH_MX1ADS + prescaler = prescaler&0x07; + clk = clk&0x07; + mmcsdr_clk_rate=(prescaler<<3)|clk; +#endif +#ifdef CONFIG_ARCH_MX2ADS + prescaler = prescaler&0x0f; + clk = clk&0xfff; + if(port == 1) + mmcsdr_clk_rate_2=(prescaler<<4)|clk; + else + mmcsdr_clk_rate=(prescaler<<4)|clk; + +#endif +} + +void _MMCSD_SetClk(int mode,int port) +{ +#ifdef CONFIG_ARCH_MX1ADS + if(mode == MMCSD_HIGH_SPEED) + { + if(cur_perclk2<20) + { + _MMCSD_ClockSet(0,0,0); + } + else + { + _MMCSD_ClockSet(cur_perclk2/20-1,1,0); + } + } + else + { + _MMCSD_ClockSet(7,7,0); + } +#endif +#ifdef CONFIG_ARCH_MX2ADS + if(mode == MMCSD_HIGH_SPEED) + { + if(cur_perclk2<20) + { + _MMCSD_ClockSet(0,1,port); + } + else + { + _MMCSD_ClockSet(0,cur_perclk2/20+1,port); + } + } + else + { + _MMCSD_ClockSet(8,0xa,port);//if perclk2 is about 20M + } + TRACE("clkrate=0x%x ,perclk2=0x%x \n",mmcsdr_clk_rate,cur_perclk2); +#endif +} +/****************************************************************************** + * Function Name: _MMCSD_PinConfig + * + * Input: + * + * Value Returned: + * + * Description: + * this routine sets GPIO registers. + * + *Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + ******************************************************************************/ + +static void _MMCSD_get_cur_perclk2(void) +{ +#ifdef CONFIG_ARCH_MX1ADS + cur_perclk2 = *(u32 *)CRM_PCDR; + cur_perclk2 = (cur_perclk2&0x000000F0)>>4; + cur_perclk2 = 96/(cur_perclk2+1); + +#endif +#ifdef CONFIG_ARCH_MX2ADS + cur_perclk2 = _reg_CRM_PCDR; + cur_perclk2 = (cur_perclk2&0x03c00000)>>22; + cur_perclk2 = 128/(cur_perclk2+1); + +#endif +} +void _MMCSD_PinConfig(void) +{ + _MMCSD_get_cur_perclk2(); +#ifdef CONFIG_ARCH_MX1ADS + *(u32 *)DBMX1_GIUS_B &= 0xFFFFC0FF; + *(u32 *)DBMX1_GPR_B &= 0xFFFFC0FF; + *(u32 *)DBMX1_PUEN_B |= 0x00003f00; +#endif + +#ifdef CONFIG_ARCH_MX2ADS + _reg_GPIO_DDIR(GPIOE) |= 0x00fc0000;//0x3f000000; + _reg_GPIO_GIUS(GPIOE) &= 0xff03ffff; + _reg_GPIO_GPR(GPIOE) &= 0xff03ffff; + _reg_GPIO_PUEN(GPIOE) |= 0x00fc0000; + + //add for SD2 pb4~pb9 pb7-dat3,pb9-clk + _reg_GPIO_DDIR(GPIOB) |= 0x000003f0; + _reg_GPIO_GIUS(GPIOB) &= ~0x000003f0; + _reg_GPIO_GPR(GPIOB) &= ~0x000003f0; + _reg_GPIO_PUEN(GPIOB) |= 0x000003f0; + +#endif +} +void _MMCSD_64M_MMC_PinConfig(void) +{ + _MMCSD_get_cur_perclk2(); +#ifdef CONFIG_ARCH_MX2ADS + //pin pe18~23,18,19,20,22 up, 21-dat3,23-clk + _reg_GPIO_DDIR(GPIOE) |= 0x00fc0000; + _reg_GPIO_GIUS(GPIOE) &= 0xff03ffff; + _reg_GPIO_GPR(GPIOE) &= 0xff03ffff; + _reg_GPIO_PUEN(GPIOE) |= 0x005c0000; +// _reg_GPIO_PUEN(GPIOE) &= 0xff5fffff; + + //add for SD2 pb4~pb9 pb7-dat3,pb9-clk + _reg_GPIO_DDIR(GPIOB) |= 0x000003f0; + _reg_GPIO_GIUS(GPIOB) &= ~0x000003f0; + _reg_GPIO_GPR(GPIOB) &= ~0x000003f0; + _reg_GPIO_PUEN(GPIOB) |= 0x00000170; + _reg_GPIO_PUEN(GPIOB) &= 0xfffffd7f; + + +#endif + //pb8~13, 11-dat3,12-clk,13-cmd +#ifdef CONFIG_ARCH_MX1ADS + *(u32 *)DBMX1_DDIR_B |= 0x00003F00; // Enable SDHC's port to Output + *(u32 *)DBMX1_GIUS_B &= 0xFFFFC0FF; + *(u32 *)DBMX1_GPR_B &= 0xFFFFC0FF; + *(u32 *)DBMX1_PUEN_B |= 0x00003700; + + *(u32 *)DBMX1_PUEN_B &=0xfffff7ff;//Karen modify it for MMC test + + + +#endif +} +/************************************************ + +put content to STR_STP_CLK + U32 Clk_en = set the clk to start or stop + 0x6: start MMC clk + 0x5: stop MMC clk + +************************************************/ +void Start_Stop_Clk(u32 Clk_en,int port) +{ + //when the clk is STARTED check whether the MMC is enable and reset is not set + if(((Clk_en&0x2)!=0)&&((Clk_en&0x8)==0)&&((Clk_en&0x4)!=0)) + { +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + { + mmcsdr_str_stp_clk_2 &= ~MMCSD_CLOCK_MASK; + mmcsdr_str_stp_clk_2 |= Clk_en; + while ( ((mmcsdr_status_2)&0x100) == 0 );//check the status if the clock do not start + } + else + { + mmcsdr_str_stp_clk &= ~MMCSD_CLOCK_MASK; + mmcsdr_str_stp_clk |= Clk_en; + while ( ((mmcsdr_status)&0x100) == 0 );//check the status if the clock do not start + } +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_str_stp_clk &= ~MMCSD_CLOCK_MASK; + mmcsdr_str_stp_clk |= Clk_en; + while ( ((mmcsdr_status)&0x100) == 0 );//check the status if the clock do not start +#endif + //when the clk is STOPPED, check whether the MMC is enable and reset is not set + } + else if(((Clk_en&0x1)!=0)&&((Clk_en&0x8)==0)&&((Clk_en&0x4)!=0)) + { +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + { + mmcsdr_str_stp_clk_2 &= ~MMCSD_CLOCK_MASK; + mmcsdr_str_stp_clk_2 |= Clk_en; + while ( ((mmcsdr_status_2) & 0x100) != 0 );//check the status if the clock is still running + } + else + { + mmcsdr_str_stp_clk &= ~MMCSD_CLOCK_MASK; + mmcsdr_str_stp_clk |= Clk_en; + while ( ((mmcsdr_status) & 0x100) != 0 );//check the status if the clock is still running + } +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_str_stp_clk &= ~MMCSD_CLOCK_MASK; + mmcsdr_str_stp_clk |= Clk_en; + while ( ((mmcsdr_status) & 0x100) != 0 );//check the status if the clock is still running +#endif + } + //reset or enable the syste + else + { +#ifdef CONFIG_ARCH_MX2ADS + if(port == 1) + { + mmcsdr_str_stp_clk_2 &= ~MMCSD_CLOCK_MASK; + mmcsdr_str_stp_clk_2 |= Clk_en; + } + else + { + mmcsdr_str_stp_clk &= ~MMCSD_CLOCK_MASK; + mmcsdr_str_stp_clk |= Clk_en; + } +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_str_stp_clk &= ~MMCSD_CLOCK_MASK; + mmcsdr_str_stp_clk |= Clk_en; +#endif + + } +} + diff -Nru src.org/drivers/mx1mmc/mmc_main.c src/drivers/mx1mmc/mmc_main.c --- src.org/drivers/mx1mmc/mmc_main.c Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/mmc_main.c Wed Oct 12 22:48:05 2005 @@ -0,0 +1,3144 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2002 Motorola Semiconductors HK Ltd + * + */ + + +/****************************************************************************** + * + * Copyright (C) 2001, Motorola All Rights Reserved + * + * File Name: mmcsd.c + * + * Progammers: Yiwei Zhao + * + * Date of Creations: 30 DEC,2001 + * + * Synopsis: + * + * Modification History: + * 30 DEC, 2001 + * 24,Dec,2003 Karen Kang + *****************************************************************************/ +#ifndef __KERNEL__ +# define __KERNEL__ +#endif +//#ifndef MODULE +//# define MODULE +//#endif +#define TESTING_PAGE (1024*1024*40/512) +#define MMCSD_TEST_PAGE_NUM 8 + +#include +#include +#include +#include /* error codes */ +#include /* everything... */ +#include /* O_ACCMODE */ +#include /* HDIO_GETGEO */ +#include +#include +#include +#include +#include +#include /* printk() */ +#include +#include +#include +#include +#include +#include +#include +#include +#include /* size_t */ +#include +#include +#include +#include + +#include +#include //for proc +//#include +#include +#include + +#include +#include +#include +#include +#include /* cli(), *_flags */ +#include + +#include +#include + +/*These symbols in that must be defined in advance.*/ +#define DEVICE_NR(device) MINOR(device) +#define DEVICE_NAME "mmc" /* name for messaging */ +#define DEVICE_NO_RANDOM /* no entropy to contribute */ + +#include + +#ifdef CONFIG_ARCH_MX1ADS +#include "dbmx1_dma.h" +#endif +#include "mmc_def.h" +#include "mmc_main.h" /* local definitions */ + +#ifdef LINUX_20 +# error "This module can't run with Linux-2.0" +#endif + +#ifdef CONFIG_PM +#define PM_OPT " [pm]" +#else +#define PM_OPT "" +#endif + +/* + * if partition is considered then HAVE_BLKPG_H should be defined. + */ +#include /* blk_ioctl() */ + +/* + * variables will be initialized in init function. + */ +MMCSD_Dev *g_mmcsd_devices = NULL; +u8 g_mmcsd_cur_device = 0xff; +u8 g_mmcsd_num = 0; +u8 g_mmcsd_cmd[2] = {0,0}; +MMCSD_Lock g_selected_lock[2]; +int g_mmcsd_major; +int g_mmcsd_presence = 0; +volatile u32 g_mmcsd_status =0; + +static devfs_handle_t devfs_handle = NULL; //devfs + +/* Function declarations */ + + +static int mmcsd_open(struct inode *inode, struct file *filp); + +static int mmcsd_release(struct inode *inode, struct file *filp); + +static int mmcsd_revalidate(kdev_t dev); + +static MMCSD_Dev *mmcsd_locate_device(const struct request *req); + +void mmcsd_request_handler(request_queue_t * q); + +static int mmcsd_data_transfer(MMCSD_Dev *device,struct request *req); + +static int mmcsd_read( MMCSD_Dev *device, char * buffer, + u32 sector, u32 nr_sector); + +static int mmcsd_write( MMCSD_Dev *device, char * buffer, + u32 sector, u32 nr_sector); + +static int mmcsd_sector_erase(MMCSD_Dev *device, MMCSD_Blks *blks); + +MMCSD_STATUS mmcsd_ReadBlock(MMCSD_Dev *device,u32 start_addr,u16 nsects, u8 *buff); + +MMCSD_STATUS mmcsd_ReadSingleBlock(MMCSD_Dev *device,u32 addr,u8 * buff); + +MMCSD_STATUS mmcsd_DMA_ReadSingleBlock(MMCSD_Dev *device,u32 addr,u8 * buff); + +int mmcsd_DmaStartTransfer(MMCSD_Dev *device,u8 * buff,u32 counter, u8 mode,u8 is_4_bit); + +void mmcsd_dma_handler(void); + +//void mmcsd_tasklet(void); + +static int mmcsd_ioctl(struct inode *inode,struct file *filp,unsigned command,unsigned long argument); + +static int mmcsd_write_protect(MMCSD_Dev *device,u32 addr, char is_set); + +static int mmcsd_passwd_cmd(MMCSD_Dev * device, MMCSD_PWD *pwd); + +static int mmcsd_is_writeprotection(MMCSD_Dev *device); + +void mmcsd_irq_handler(int irq,void * data, struct pt_regs * pt); + +static int mmcsd_getMBR(MMCSD_Dev * device); + +static int mmcsd_check_status(MMCSD_Dev *device,u32 *pstate); + +static void mmcsd_dma_isr(void * arg); + +static void mmcsd_dma_err_isr(int error_type); + +MMCSD_STATUS mmcsd_write_blks(MMCSD_Dev *device); + +MMCSD_STATUS mmcsd_dma_write_blks(MMCSD_Dev *device); + +void mmcsd_free_buffer(MMCSD_Dev *device); + +void _mmcsd_16_big_2_little(u8 *buf, u32 size); + +void _mmcsd_cp_16_little_2_big(u8 *src,u8 *target, int size); + +void mmcsd_delay(u32 delay); + +static int handle_pm_event(struct pm_dev *dev, pm_request_t rqst, void *data); + +/* Set up our tasklets. */ + +static struct block_device_operations mmcsd_bdops = { +open: mmcsd_open, +release: mmcsd_release, +ioctl: mmcsd_ioctl, +revalidate: mmcsd_revalidate, +}; + +#ifndef MODULE +extern int errno; +#endif + + +extern unsigned char gSDWriteProtect; + +static char g_socket1_info; +#define SD_SOCKET_NO_CARD 0x01 +#define SD_SOCKET_CARD 0x02 + +#ifdef CONFIG_ARCH_MX2ADS +static char gSDumounted; +static devfs_handle_t devfs_handle1 = NULL; //devfs +void mmcsd_irq_handler_2(int irq,void * data, struct pt_regs * pt); +static void mmcsd_dma_isr_1(void * arg); +#endif + +/* + ******************************************************************************** + * Description: + * Card detect function + * + * History: + * 03-Feb-04 Aaron Add Card detection for MX1 silicon 2.0 (Use PB17) + ******************************************************************************** + */ +void mmcsd_socket1_irq_handler(int irq, void *dev_id, struct pt_regs * regs) +{ + u32 status,trigger; +#ifdef CONFIG_ARCH_MX1ADS + status = *(u32 *)DBMX1_ISR_B; + trigger = *(u32 *)DBMX1_ICR2_B; + if((status & 0x00100000)==0x00100000) //get PortB20 int + { + if((trigger & 0x00000300)==0x00000200) //it is positive level + { + g_socket1_info = SD_SOCKET_NO_CARD; + *(u32 *)DBMX1_ICR2_B |= 0x00000300; //set it to be negative level trigger detect card withdraw + printk("A card is withdrawn from socket1 \n"); + } + else if((trigger & 0x00000300)==0x00000300) //it is negative level + { + g_socket1_info = SD_SOCKET_CARD; + *(u32 *)DBMX1_ICR2_B &= ~0x00000100; // config as positive level trigger10 + *(u32 *)DBMX1_ICR2_B |= 0x00000200; ;//set it to be positive level trigger detect card insert + printk("A card is inserted in socket1 \n"); + } + } +#endif +#ifdef CONFIG_ARCH_MX2ADS + status = _reg_GPIO_ISR(GPIOD); + trigger = _reg_GPIO_ICR2(GPIOD); + if((status & 0x02000000)==0x02000000) //get PortB16 int + { + if((trigger & 0x000C0000)==0x00080000)//it is positive level now + { + g_socket1_info = SD_SOCKET_NO_CARD; + _reg_GPIO_ICR2(GPIOD) |= 0x000C0000; //set it to be negative level trigger detect card withdraw + printk("A card is withdrawn from socket1 \n"); + } + if((trigger & 0x000C0000)==0x000C0000)//it is negative level now + { + g_socket1_info = SD_SOCKET_CARD; + _reg_GPIO_ICR2(GPIOD) &= ~0x00040000; // config as positive level trigger10 + _reg_GPIO_ICR2(GPIOD) |= 0x00080000;//set it to be positive level trigger detect card insert + printk("A card is inserted in socket1 \n"); + } + } +#endif + _mmcsd_socket1_clear_irq(); +} + +static int mmcsd_proc_output (char *buf) +{ + char *p; + unsigned long flags; + save_flags(flags); + cli(); + p = buf; + //Add to proc to indicate which card in which socket + + if(g_socket1_info == SD_SOCKET_NO_CARD) + { + p += sprintf(p, "socket1 : nocard \n"); + // p += sprintf(p, "socket2 : nocard \n"); + } + else if(g_socket1_info == SD_SOCKET_CARD) + { + p += sprintf(p, "socket1 : card \n"); + } + restore_flags(flags); + return p - buf; + +} + +static int mmcsd_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + + int len = mmcsd_proc_output(page); + if (len <= (off+count)) + *eof = 1; + *start = page + off; + len -= off; + if (len>count) + len = count; + if (len<0) + len = 0; + return len; +} +/****************************************************************************** + * Function Name: mmcsd_init + * + * Input: None. + * Value Returned: 0: success; + * others failure; + * + * Description: This is the initialization routine for the driver. And this function + * will be called while the module being installed. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +#ifdef MODULE +int init_module(void) +#else +int __init mmcsd_init(void) +#endif +{ + + int ret,i; + printk("MMC device driver version 0.4.0\n"); + TRACE("\n Begin initialize mmcsd module "); + /***************************************************** + * Register the block driver. + *****************************************************/ +#ifdef CONFIG_ARCH_MX2ADS + gSDumounted = 0; +#endif + + g_mmcsd_major = MMCSD_MAJOR; + ret = devfs_register_blkdev(g_mmcsd_major, "mmc", &mmcsd_bdops); + if (ret < 0) + { + FAILED(" can't get major %d\n",MMCSD_MAJOR); + return ret; + } + + if(g_mmcsd_major == 0) + { + g_mmcsd_major = ret; /* dynamic */ + } + devfs_handle=devfs_register(NULL,"mmc",DEVFS_FL_DEFAULT,g_mmcsd_major,0, + S_IFBLK | S_IRUGO | S_IWUGO,&mmcsd_bdops,NULL); + +#ifdef CONFIG_ARCH_MX2ADS + devfs_handle1 = devfs_register(NULL, "mmc1",DEVFS_FL_DEFAULT,g_mmcsd_major,1, + S_IFBLK | S_IRUGO | S_IWUGO,&mmcsd_bdops,NULL); +#endif + + read_ahead[g_mmcsd_major] = MMCSD_READ_AHEAD;/* in sectors */ + + /******************************************************* + * Allocate space for each devices. + *******************************************************/ + + g_mmcsd_num = MMCSD_DEVICE_NUM; + + g_mmcsd_devices = kmalloc((g_mmcsd_num*sizeof(MMCSD_Dev)), GFP_KERNEL); + if (!g_mmcsd_devices) + { + goto fail_init; + } + memset(g_mmcsd_devices,0,(g_mmcsd_num * sizeof(MMCSD_Dev))); + for (i=0; i < g_mmcsd_num; i++) + { + spin_lock_init(&(g_mmcsd_devices[i].lock)); + spin_unlock(&(g_mmcsd_devices[i].lock)); + init_waitqueue_head(&(g_mmcsd_devices[i].select_wait)); + sema_init(&(g_mmcsd_devices[i].sema),1); + g_mmcsd_devices[i].dma_channel = 0xFFFFFFFF; + + } + g_selected_lock[0].device = NULL; + g_selected_lock[1].device = NULL; + + /******************************************************* + * Allocate request queue for each device. + *******************************************************/ + /* + for(i = 0;i < g_mmcsd_num; i++) + { + + blk_init_queue(&(g_mmcsd_devices[i].queue), mmcsd_request_handler); + blk_queue_headactive(&(g_mmcsd_devices[i].queue),0); + } + */ + + blk_init_queue(BLK_DEFAULT_QUEUE(g_mmcsd_major),mmcsd_request_handler); + + /****************************************************** + * Regist Interrupt Service Routine + ******************************************************/ + + ret = request_irq(MMCSD_IRQ, + mmcsd_irq_handler, + SA_INTERRUPT, + "mmc", + "mmc"); + + if(ret) + { + TRACE("request irq error"); + goto fail_init; + } +#ifdef CONFIG_ARCH_MX2ADS + ret = request_irq(MMCSD2_IRQ, + mmcsd_irq_handler_2, + SA_INTERRUPT, + "mmc1", + "mmc1"); +#endif + if(ret) + { + TRACE("request irq error"); + goto fail_init; + } + /***************************************************** + *setting for auto-mount/umount + ******************************************************/ + g_socket1_info = SD_SOCKET_NO_CARD; + ret = request_irq(MMCSD_SOCKET1_INT, + mmcsd_socket1_irq_handler, + SA_INTERRUPT, + "mmc", + "mmc"); +#ifdef CONFIG_ARCH_MX2ADS + ret = request_irq(MMCSD_SOCKET1_INT, + mmcsd_socket1_irq_handler, + SA_INTERRUPT|SA_SHIRQ, + "mmc", + "mmc"); +#endif + if(ret) + { + TRACE("request irq error"); + goto fail_init; + } + _mmcsd_socket1_irq_set(); + create_proc_read_entry ("mmc", 0, 0, mmcsd_read_proc, NULL); + /****************************************************** + * Regist PM device. + ******************************************************/ + + pm_register(PM_SYS_DEV, PM_SYS_UNKNOWN, handle_pm_event); + + /****************************************************** + * Pin Configuration + * + *****************************************************/ + + _MMCSD_64M_MMC_PinConfig(); + + /****************************************************** + * LOOP FOR THE MAXIMUM NUMBER OF CARD SLOTS + ******************************************************/ + for ( i = 0 ; i < MMCSD_DEVICE_NUM ; i++ ) + { + g_mmcsd_devices[i].card_state= MMCSD_NOTREADY; + g_mmcsd_devices[i].card_rca = 1; + } + + + return 0; + + /****************************************************** + * Enable SDHC module + ******************************************************/ + +fail_init: + read_ahead[g_mmcsd_major] = 0; + if (g_mmcsd_devices) + { + kfree(g_mmcsd_devices); + } + free_irq(MMCSD_IRQ,"mmc"); +#ifdef CONFIG_ARCH_MX2ADS + free_irq(MMCSD2_IRQ,"mmc1"); + free_irq(MMCSD_SOCKET1_INT,"mmc"); + devfs_unregister(devfs_handle1); +#endif + devfs_unregister_blkdev(g_mmcsd_major, "mmc"); + devfs_unregister(devfs_handle); + + return ret; +} + +/****************************************************************************** + * Function Name: mmcsd_cleanup + * + * Input: None. + * Value Returned: 0: success; + * others failure; + * + * Description: + * this routine will clean up mmcsd module. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +#ifdef MODULE +void cleanup_module(void) +#else +int __exit mmcsd_cleanup(void) +#endif +{ + + pm_unregister_all(handle_pm_event); + + read_ahead[g_mmcsd_major] = 0; + if (g_mmcsd_devices) + { + kfree(g_mmcsd_devices); + } + free_irq(MMCSD_IRQ,"mmc"); +#ifdef CONFIG_ARCH_MX2ADS + free_irq(MMCSD2_IRQ,"mmc1"); + + free_irq(MMCSD_SOCKET1_INT,"mmc"); + remove_proc_entry("mmc", NULL); +#endif + devfs_unregister_blkdev(g_mmcsd_major, "mmc"); + devfs_unregister(devfs_handle); +#ifdef CONFIG_ARCH_MX2ADS + devfs_unregister(devfs_handle1); +#endif + return 0; + +} + +/****************************************************************************** + * Function Name: mmcsd_revalidate + * + * Input: None. + * Value Returned: 0: success; + * others failure; + * + * Description: This routine will revalidate device. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +static int mmcsd_revalidate(kdev_t dev) +{ + return 0; +} +/****************************************************************************** + * Function Name: mmcsd_open + * + * Input: None. + * Value Returned: 0: success; + * others failure; + * + * Description: This routine will initilialize a device. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +static int mmcsd_open(struct inode *inode, struct file *filp) +{ + + MMCSD_Dev *device; + int num,i,ret,major; + int channel=-1; + + TRACE("mmcsd_open is called"); + /********************************************************************* + * Check the device numer + *********************************************************************/ + num = MINOR(inode->i_rdev); + major = MAJOR(inode->i_rdev); + gSDWriteProtect = 0; + +#ifdef CONFIG_ARCH_MX2ADS + if(num == 0) + _reg_CRM_PCCR0 |= 0x0200;//enable sdhc1 clk + else if(num == 1) + _reg_CRM_PCCR0 |= 0x0400;//enable sdhc2 clk + +#endif + + if(!filp) + { + TRACE(" called without filp"); + return -EIO; + } + + if(num > g_mmcsd_num) + { + return -ENODEV; + } + device = &g_mmcsd_devices[num]; + //Karen add for MX21 + device->port = num; + /***************************************************************** + * Initialize the device + *****************************************************************/ + spin_lock(&device->lock); + down_interruptible(&(device->sema)); + + ret = 0; + if(device->usage == 0) + { + /****************************************************** + * Initialize Cards + ******************************************************/ + _MMCSD_64M_MMC_PinConfig(); + _MMCSD_InitSDHC(num); + ret = _MMCSD_InitMMC(num); + if(ret) + { + FAILED("_MMC_Init error"); + goto fail_malloc; + // return -1; + } + ret = _MMCSD_GetInfo(device); // Implement + if(ret) + { + FAILED("_MMCSD_GetInfo error!"); + spin_unlock(&device->lock); + up(&(device->sema)); + goto fail_malloc; + // return -1; + } + ret = _MMCSD_SetSectLen(device); // Implement + if(ret) + { + FAILED(" _MMCSD_SetSectLen error!"); + spin_unlock(&device->lock); + up(&(device->sema)); + goto fail_malloc; + // return -1; + } + device->blksize = MMCSD_MINIMUM_BLK_SIZE; + blk_size[major] = kmalloc(sizeof(int), GFP_KERNEL); + if (!blk_size[major]) + goto fail_malloc; + blk_size[major][num] = device->dev_size/1024;/* in KB */ + + blksize_size[major]= kmalloc(sizeof(int), GFP_KERNEL); + if (!blksize_size[major]) + goto fail_malloc; + blksize_size[major][num] = device->blksize;/* in B*/ + + hardsect_size[major]=kmalloc(sizeof(int), GFP_KERNEL); + if (!hardsect_size[major]) + goto fail_malloc; + hardsect_size[major][num] = device->blksize;/* in B*/ + + ret = _MMCSD_SelectDeselectCard(device->card_rca,device->port); + if(ret) + { + FAILED("Select error"); + device->card_state = MMCSD_NOTREADY; + goto fail_malloc; + } + /*********************************************************** + * Initialize DMA + ***********************************************************/ +#ifdef CONFIG_ARCH_MX1ADS + for(channel = 2; channel < 11; channel++) + { + if((ret = request_dma(channel, "mmc"))==0) + { + //TRACE("Get Channel %ld",channel); + break; + } + } + if(channel >10) goto fail_malloc; + + device->dma_channel = channel; + request_dma_intr(channel,(void *)mmcsd_dma_isr,(void *)mmcsd_dma_err_isr); +#endif +#ifdef CONFIG_ARCH_MX2ADS + if(num == 1) + { + mx_request_dma(&channel,"mmc1"); + (device->dma).callback = (void *)mmcsd_dma_isr_1; + } + else + { + mx_request_dma(&channel,"mmc"); + (device->dma).callback = (void *)mmcsd_dma_isr; + } + device->dma_channel = channel; +#endif + /*********************************************************** + * Initialize buff_pool for write operations. + **********************************************************/ + + device->buff_pool[0]=kmalloc(sizeof(u8)*(device->blksize)*MMCSD_MAX_MULTI_BLK, + GFP_KERNEL|GFP_DMA); +#ifdef MMCSD_DMA_ENDIAN_ERR + device->tmp_pool[0]=kmalloc(sizeof(u8)*(device->blksize)*MMCSD_MAX_MULTI_BLK, + GFP_KERNEL|GFP_DMA); +#endif + + if(device->buff_pool[0]==NULL) + { + FAILED("Allocate Buffer failed"); + goto fail_malloc; + } + for(i = 0; i< MMCSD_MAX_MULTI_BLK;i++) + { + device->buff_pool[i] = device->buff_pool[0]+(device->blksize)*i; +#ifdef MMCSD_DMA_ENDIAN_ERR + device->tmp_pool[i] = device->tmp_pool[0]+(device->blksize)*i; +#endif + } + device->cur_sec = 0xFFFFFFFF; + device->cur_num = 0; + device->busy = 0; + + device->bit_width = 0; + _MMCSD_SetClk(MMCSD_HIGH_SPEED,num); + + /*********************************************************** + * Get MBR + ***********************************************************/ + + ret = mmcsd_getMBR(device); + if(ret) + { + FAILED("mmcsd_getMBR error!"); + goto fail_malloc; + } + /*********************************************************** + * Detect wether it's read only + ***********************************************************/ + + ret = 0; + } + (device->usage)++; + spin_unlock(&device->lock); + up(&(device->sema)); + MOD_INC_USE_COUNT; + return ret; + +fail_malloc: + if (blk_size[major]) kfree(blk_size[major]); + blk_size[major] = NULL; + if (blksize_size[major]) kfree(blksize_size[major]); + blksize_size[major] = NULL; + if (hardsect_size[major]) kfree(hardsect_size[major]); + hardsect_size[major] = NULL; +#ifdef CONFIG_ARCH_MX1ADS + if(device->dma_channel!= 0xFFFFFFFF) + free_dma(device->dma_channel); +#endif +#ifdef CONFIG_ARCH_MX2ADS + if(device->dma_channel!= 0xFFFFFFFF) + mx_free_dma(device->dma_channel); +#endif + if(device->buff_pool[0]!=NULL) + kfree(device->buff_pool[0]); + + spin_unlock(&device->lock); + up(&(device->sema)); + return MMCSD_ERROR; + +} + +/****************************************************************************** + * Function Name: mmcsd_release + * + * Input: None. + * Value Returned: 0: success; + * others failure; + * + * Description: This routine will release the device. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +static int mmcsd_release(struct inode *inode, struct file *filp) +{ + MMCSD_Dev * device; + int num; + u32 state; + MMCSD_STATUS ret; + + TRACE("mmcsd_release is called"); + /********************************************************************* + * Check the device numer + *********************************************************************/ + num = MINOR(inode->i_rdev); + + if(num > g_mmcsd_num) + { + return -ENODEV; + } + device = &g_mmcsd_devices[num]; + + /***************************************************************** + * Initialize the device + *****************************************************************/ + spin_lock(&device->lock); + down_interruptible(&(device->sema)); + + (device->usage)--; + + if(device->usage == 0) + { + fsync_dev(inode->i_rdev); + +#ifdef MMCSD_WRITE_DMA + mmcsd_dma_write_blks(device); +#else + mmcsd_write_blks(device); +#endif + state =MMCSD_TRANSFER; + mmcsd_check_status(device,&state); + + ret = _MMCSD_SelectDeselectCard(0,device->port); + if(ret) + { + TRACE("Select error"); + device->card_state = MMCSD_NOTREADY; + // g_selected_lock.device = NULL; + // spin_unlock(g_selected_lock.lock); + } + + // _MMCSD_StopClk(); + // Start_Stop_Clk(1); + g_selected_lock[0].device = NULL; + g_selected_lock[1].device = NULL; + +#ifdef CONFIG_ARCH_MX1ADS + if(device->dma_channel!= 0xFFFFFFFF) + free_dma(device->dma_channel); +#endif +#ifdef CONFIG_ARCH_MX2ADS + if(device->dma_channel!= 0xFFFFFFFF) + mx_free_dma(device->dma_channel); +#endif + if(device->buff_pool[0]!=NULL) + kfree(device->buff_pool[0]); +#ifdef MMCSD_DMA_ENDIAN_ERR + if(device->buff_pool[0]!=NULL) + kfree(device->buff_pool[0]); +#endif + } + MOD_DEC_USE_COUNT; + + spin_unlock(&device->lock); + up(&(device->sema)); + + return 0; +} + +/****************************************************************************** + * Function Name: mmcsd_locate_device + * + * Input: + * q: the pointer to request structure. + * + * Value Returned: + * NULL: no device structure found; + * pointer: to MMCSD_Device structure. + * + * Description: + * this routine will return corresponding MMCSD device structure of the + * request. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +static MMCSD_Dev *mmcsd_locate_device(const struct request *req) +{ + int devno; + + devno = DEVICE_NR(req->rq_dev); + if(devno >= g_mmcsd_num) + { + TRACE("\nmmcsd_locate_device: devno = %d", devno); + return NULL; + } + return(&g_mmcsd_devices[devno]); +} + +/****************************************************************************** + * Function Name: mmcsd_request_handler + * + * Input: + * q: the request queue the handler will process + * + * Value Returned: + * NO. + * + * Description: + * This is the request handler for read/write operations. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +void mmcsd_request_handler(request_queue_t * q) +{ + MMCSD_Dev * device; + struct request *req; + int ret; + + /*********************************************************************** + * Locate the device + ***********************************************************************/ + + device = mmcsd_locate_device(blkdev_entry_next_request(&(q->queue_head))); + if(!device) + { + TRACE(" mmcsd_locate_device error"); + return ; + } + + device->busy = 1; + + /********************************************************************** + * process the request quueue. + **********************************************************************/ + + while(!list_empty(&q->queue_head)) + { + req = blkdev_entry_next_request(&(q->queue_head)); + blkdev_dequeue_request(req); + spin_unlock_irq(&io_request_lock); + + down_interruptible(&(device->sema)); + do { + //TRACE("New Request coming"); + + ret = mmcsd_data_transfer(device, req); + + + }while(end_that_request_first(req,ret,DEVICE_NAME)); + up(&(device->sema)); + + spin_lock_irq(&io_request_lock); + end_that_request_last(req); + + } + device->busy = 0; + return ; +} + +/****************************************************************************** + * Function Name: mmcsd_data_transfer + * + * Input: + * device: the device that the transfer will take place. + * req: the request that will be processed. + * + * Value Returned: + * 1: success. + * 0: failure. + * + * Description: + * this routine will be start the read/write transfer. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +static int mmcsd_data_transfer(MMCSD_Dev *device,struct request *req) +{ + int ret; + + + + /* Looks good, do the transfer. */ + switch(req->cmd) { + + case READ: + + ret = mmcsd_read(device, + req->buffer, + req->sector+device->lba_sec_offset, + req->current_nr_sectors); + /* + if(req->sector ==1) + { + // For Testing + TRACE("Reading TESTING:"); + _mmcsd_test_reading_pages(device); + } + */ + if(ret) + return 0; + else + return 1; + + case WRITE: + + ret = mmcsd_write(device, + req->buffer, + (req->sector+device->lba_sec_offset), + req->current_nr_sectors); + if(ret) + return 0; + else + return 1; + + default: + + return 0; + } + +} + +/****************************************************************************** + * Function Name: mmcsd_read + * + * Input: + * device: the device read from + * buffer: memory area for I/O transfer. + * sector: first sector number; + * nr_sector: number of the sectos + * + * Value Returned: + * 0: success. + * 1: failure. + * + * Description: + * this routine will read indicated sectors into memory + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +static int mmcsd_check_status(MMCSD_Dev *device,u32 *pstate) +{ + MMCSD_STATUS ret = MMCSD_OK; + u32 state; + int i; + + state = *pstate; + + g_mmcsd_cmd[device->port]=MMCSD_CMD13; + + i = 0xFFFFFFFF; + while(i--) + { + //TRACE("SendStatus... 0x%lx",*mmcsdr_status); + ret = _MMCSD_SendStatus(device->card_rca,pstate,device->port); + if(ret) // the command failed. + { + mmcsd_delay(0xFF); + //TRACE("Card Status = 0x%08X", *pstate); + } + else + { + if(((*pstate)&MMCSD_STATUS_STATE) != state) + { + mmcsd_delay(0xFF); + } + else + { + if(state==MMCSD_TRANSFER) + { + if(((*pstate)&0x100)==0) + continue; + } + break; + } + TRACE("state = 0x%lx,request is 0x%lx",(unsigned long)*pstate,(unsigned long)state); + } + //TRACE("try again..(SendStatus... 0x%lx) %d",*mmcsdr_status,i); + + } + //TRACE("return with %d",ret); + return ret; +} + +static int mmcsd_read( MMCSD_Dev *device, char * buffer, + u32 sector, u32 nr_sector) +{ + int ret; + u32 start_addr,state; + + start_addr = sector * MMCSD_FS_SECTOR_SIZE; + + g_selected_lock[device->port].device = device; + //TRACE("read from 0x%0lX, number:0x%0lX", sector, nr_sector); + + state = MMCSD_TRANSFER; + ret = mmcsd_check_status(device,&state); + if(ret) + { + FAILED("Check Status failed!"); + return 1; + } + + /******************************************************************** + * Get the Lock for seclected device + *******************************************************************/ + + ret = _MMCSD_SetBlockLen(MMCSD_MINIMUM_BLK_SIZE,1,device->port); + if(ret) + { + FAILED("Set Block Len failed, ret = 0x%x",ret); + return 1; + } + + state = MMCSD_TRANSFER; + ret = mmcsd_check_status(device,&state); + + + /******************************************************************** + * Begin to Read + *******************************************************************/ + + if((ret=(mmcsd_ReadBlock(device,start_addr, nr_sector, buffer)))!=MMCSD_OK) + { + FAILED(" ReadBlock error"); + device->card_state = MMCSD_NOTREADY; + //g_selected_lock.device = NULL; + //spin_unlock(g_selected_lock.lock); + return 1; + } + + device->card_state = MMCSD_STANDBY; + + return 0; +} + +/****************************************************************************** + * Function Name: mmcsd_write + * + * Input: + * device: the device write to + * buffer: memory area for I/O transfer. + * sector: first sector number; + * nr_sector: number of the sectos + * + * Value Returned: + * 0: success. + * 1: failure. + * + * Description: + * this routine will write data into indicated sectors. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +static int mmcsd_write( MMCSD_Dev *device, char * buffer, + u32 sector, u32 nr_sector) +{ + int ret; + u32 i; + + TRACE(" write to 0x%lx, number:0x%lx", (unsigned long)sector, (unsigned long)nr_sector); + + device->addr = sector * device->blksize; + + while (nr_sector) + { + int nr_write = min(nr_sector, (MMCSD_MAX_MULTI_BLK - device->cur_num)); + +#ifdef MMCSD_DMA_ENDIAN_ERR + _mmcsd_cp_16_little_2_big(buffer, device->tmp_pool[device->cur_num], nr_write * device->blksize); +#else + memcpy(device->buff_pool[device->cur_num], buffer, nr_write * device->blksize); +#endif + if (device->cur_num == 0) + + device->cur_num += nr_write; + device->cur_sec += nr_write; + + buffer += nr_write * device->blksize; + nr_sector -= nr_write; + + if ((nr_sector == 0) || (device->cur_num == MMCSD_MAX_MULTI_BLK)) + { +#ifdef MMCSD_WRITE_DMA + ret = mmcsd_dma_write_blks(device); +#else + ret = mmcsd_write_blks(device); +#endif + if (ret != MMCSD_OK) + { + FAILED("mmcsd_write_blk failed"); + return ret; + } + // cur_num should be zero + } + } + + return MMCSD_OK; +} + +MMCSD_STATUS mmcsd_write_blks(MMCSD_Dev *device) +{ + + int i,t,j,counter; + u32 state,ret,ret2,int_mask, temp32; + u16 temp16,*p16; + u32 addr; + u32 burst_len=8; + + if(device->cur_num == 0) + { + mmcsd_free_buffer(device); + return MMCSD_OK; + } + + ret=ret2=MMCSD_OK; + + TRACE("enter mmcsd_write_blks....."); + + g_selected_lock[device->port].device = device; + + /************************************************************** + * Check the Card Status + **************************************************************/ + state =MMCSD_TRANSFER; + ret = mmcsd_check_status(device,&state); + if(ret) + { + mmcsd_free_buffer(device); + return ret; + } + + /************************************************************** + * Mask Interrupt + **************************************************************/ + TRACE("Disable Interrupt.."); + _MMCSD_Mask_interrupt(0x7F,&int_mask,device->port); + /** + * End of Testing + */ + + /************************************************************** + * Set Block Length + **************************************************************/ + i = 5; + while(i--) + { + ret = _MMCSD_SetBlockLen(MMCSD_MINIMUM_BLK_SIZE,device->cur_num,device->port); + if(ret) + { + TRACE("3)Set Block Len, ret = 0x%lx,state=%lx",(unsigned long)ret,(unsigned long)state); + TRACE("4)Try again...%d",i); + state = MMCSD_TRANSFER; + mmcsd_check_status(device,&state); + } + else //ret == SUCCESS! + { + break; + } + + } + if(ret) + { + mmcsd_free_buffer(device); + FAILED("5)Set Blocked Len Failed!"); + return ret; + + } + /******************************************************************** + * Begin to write + *******************************************************************/ + + + addr = device->addr; + TRACE("6)addr 0x%lx (sec 0x%lx), blks %ld", + (unsigned long)addr,(unsigned long)(addr/512),(unsigned long)(device->cur_num)); + + _MMCSD_StopClk(device->port); + + if(device->cur_num == 1) + { + if(device->bit_width == 0) + { + _MMCSD_SetCmd(MMCSD_CMD24,addr,MMCSDB_DATEN|MMCSDB_R1|MMCSDB_WRRD,device->port); + burst_len = 8; + } + else + { + _MMCSD_SetCmd(MMCSD_CMD24,addr,MMCSD_BUS_4BIT|MMCSDB_DATEN|MMCSDB_R1|MMCSDB_WRRD,device->port); + burst_len = 32; + } + g_mmcsd_cmd[device->port] = MMCSD_CMD24; + } + else + { + if(device->bit_width == 0) + { + _MMCSD_SetCmd(MMCSD_CMD25,addr,MMCSDB_DATEN|MMCSDB_R1|MMCSDB_WRRD,device->port); + burst_len = 8; + } + else + { + _MMCSD_SetCmd(MMCSD_CMD25,addr,MMCSD_BUS_4BIT|MMCSDB_DATEN|MMCSDB_R1|MMCSDB_WRRD,device->port); + burst_len = 32; + } + g_mmcsd_cmd[device->port] = MMCSD_CMD25; + } + _MMCSD_StartClk(device->port); + + ret = MMCSD_OK; + for( t=0; tcur_num; t++) + { + counter = 0; +#ifdef MMCSD_DMA_ENDIAN_ERR + p16 = (u16 *)device->tmp_pool[t]; +#else + p16 = (u16 *)device->buff_pool[t]; +#endif + while(ret == MMCSD_OK) + { +#ifdef CONFIG_ARCH_MX2ADS + if(device->port == 1) + { + g_mmcsd_status = (mmcsdr_status_2); + } + else + g_mmcsd_status = (mmcsdr_status); +#endif +#ifdef CONFIG_ARCH_MX1ADS + g_mmcsd_status = (mmcsdr_status); +#endif + if((g_mmcsd_status&0x1043)==0) + { + continue; + } + + j = 0xFF; + while(j--); + // TRACE("g_mmcsd_status = 0x%x",g_mmcsd_status); + // + if(g_mmcsd_status&0x0003) + { + TRACE("7)ERROR!--, g_mmcsd_status = %lx",(unsigned long)g_mmcsd_status); + ret = MMCSD_ERROR; + } + else if((g_mmcsd_status&0x0040)!=0) // Buffer is empty + { + // TRACE("FIFO is empty!"); + for(i = 0; i < burst_len; i++) + { + temp16 = (*p16); + temp32 = temp16; +#ifdef CONFIG_ARCH_MX2ADS + if(device->port == 1) + mmcsdr_buffer_access_2 = temp32; + else + mmcsdr_buffer_access = temp32; +#endif +#ifdef CONFIG_ARCH_MX1ADS + mmcsdr_buffer_access = temp32; +#endif + + p16++; + + } + counter += burst_len*2; + } + if(counter == device->blksize) + { + break; + } + } + if(ret!=MMCSD_OK) + break; + } + + /******************************************************* + * Write Done + *******************************************************/ + if(ret==MMCSD_OK) + { + while(1) + { +#ifdef CONFIG_ARCH_MX2ADS + if(device->port == 1) + { + g_mmcsd_status = mmcsdr_status_2; + } + else + g_mmcsd_status = mmcsdr_status; +#endif +#ifdef CONFIG_ARCH_MX1ADS + g_mmcsd_status = mmcsdr_status; +#endif + if(g_mmcsd_status&0x0007) + { + TRACE("8)ERROR! status = 0x%lx",(unsigned long)g_mmcsd_status); + ret = MMCSD_ERROR; + break; + } + else if((g_mmcsd_status&0x1000)!=0) + { + TRACE("9)Write Done! g_mmcsd_status = 0x%lx",(unsigned long)g_mmcsd_status); + ret = MMCSD_OK; + break; + } + TRACE("10)g_mmcsd_status = %lx",(unsigned long)g_mmcsd_status); + } + } + + TRACE("Enable Intr..."); + _MMCSD_Restore_Mask(int_mask,device->port); + g_mmcsd_cmd[device->port] = 0; + + if(device->cur_num>1) + { + ret2=_MMCSD_NoDataCommand(MMCSD_CMD12,device->card_rca<<16,MMCSDB_R1,device->port); + } + + // state =MMCSD_TRANSFER; + // mmcsd_check_status(device,&state); + + mmcsd_free_buffer(device); + TRACE("15)return with ret = %lx,ret2 = %lx",(unsigned long)ret,(unsigned long)ret2); + return(ret|ret2); +} + +/*! + * Dump binary data in hex + */ +static void kdump(const void *_buf, size_t len) +{ + int i; + const unsigned char *buf = (const unsigned char *)_buf; + + for (i = 0; i < len; i++) + { + printk("%02x ", *buf++); + if (i % 16 == 15) + printk("\n"); + } + printk("\n"); +} + +MMCSD_STATUS mmcsd_dma_write_blks(MMCSD_Dev *device) +{ + int i,timeleft; + u32 state,ret,ret2,int_mask = 0xFFFFFFFF; + u32 addr; + u32 status,counter; + + + if(device->cur_num == 0) + { + mmcsd_free_buffer(device); + return MMCSD_OK; + } + + + ret=ret2=MMCSD_OK; + g_selected_lock[device->port].device = device; + + /************************************************************** + * Check the Card Status + **************************************************************/ + //TRACE("Check Status"); + + state =MMCSD_TRANSFER; + ret = mmcsd_check_status(device,&state); + if(ret) + { + mmcsd_free_buffer(device); + FAILED("2)Check Error!"); + return ret; + } + + /** + * End of Testing****************************************************************** + */ + /************************************************************** + * Set Block Length + **************************************************************/ + i = 5; + while(i--) + { + // TRACE("Set Block Length"); + ret = _MMCSD_SetBlockLen(MMCSD_MINIMUM_BLK_SIZE,device->cur_num,device->port); + if(ret) + { + TRACE("3)Set Block Len, ret = 0x%lx,state=%lx",(unsigned long)ret,(unsigned long)state); + TRACE("4)Try again...%d",i); + state = MMCSD_TRANSFER; + mmcsd_check_status(device,&state); + } + else //ret == SUCCESS! + { + break; + } + } + if(ret) + { + mmcsd_free_buffer(device); + FAILED("5)Set Blocked Len Failed!"); + goto dma_write_end; + } + + state = MMCSD_TRANSFER; + ret = mmcsd_check_status(device,&state); + if(ret) + { + mmcsd_free_buffer(device); + FAILED("Check Status failed."); + goto dma_write_end; + } + + i = 10; + while(i--) + { + } + if(ret) + { + mmcsd_free_buffer(device); + FAILED("Set Bus Width Failed!"); + goto dma_write_end; + } + /******************************************************************** + * Begin to write + *******************************************************************/ + + addr = device->addr; + TRACE("*** addr 0x%lx (sect 0x%lx, %ld), %ld blks", + addr,addr/512,addr/512,device->cur_num); + + //kdump(device->buff_pool[0], device->cur_num * MMCSD_MINIMUM_BLK_SIZE); + + /************************************************************** + * Mask Interrupt + **************************************************************/ + //TRACE("Disable Interrupt"); + _MMCSD_Mask_interrupt(0x78,&int_mask,device->port); + /* + * DMA Preparation + */ + /************************************************************** + * Config DMA + **************************************************************/ + + // TRACE("DMA Configuration"); + ret = mmcsd_DmaStartTransfer(device, +#ifdef MMCSD_DMA_ENDIAN_ERR + device->tmp_pool[0], +#else + device->buff_pool[0], +#endif + MMCSD_MINIMUM_BLK_SIZE*(device->cur_num), + MMCSD_WRITE, + device->bit_width); + if(ret != MMCSD_OK) + { + FAILED("mmcsd_DmaStartTransfer failed"); + goto dma_write_end; + } + + + /************************************************************** + * Set Command + **************************************************************/ + + state =MMCSD_TRANSFER; + ret = mmcsd_check_status(device,&state); + if(ret) + { + FAILED("Check Status failed."); + } + + + // TRACE("Set Command (24/25)"); + + _MMCSD_StopClk(device->port); + if(device->cur_num == 1) + { + if(device->bit_width == 0) + { + _MMCSD_SetCmd(MMCSD_CMD24,addr,MMCSDB_DATEN|MMCSDB_R1|MMCSDB_WRRD,device->port); + } + else + { + _MMCSD_SetCmd(MMCSD_CMD24,addr,MMCSD_BUS_4BIT|MMCSDB_DATEN|MMCSDB_R1|MMCSDB_WRRD,device->port); + } + } + else + { + if(device->bit_width == 0) + { + _MMCSD_SetCmd(MMCSD_CMD25,addr,MMCSDB_DATEN|MMCSDB_R1|MMCSDB_WRRD,device->port); + } + else + { + _MMCSD_SetCmd(MMCSD_CMD25,addr,MMCSD_BUS_4BIT|MMCSDB_DATEN|MMCSDB_R1|MMCSDB_WRRD,device->port); + } + } + + // TRACE("Start Clk... Wait CMD Done."); + ret = MMCSD_OK; + _MMCSD_StartClk(device->port); + + //if((ret=_MMCSD_irq_WaitUntil(MMCSD_CMD_DONE,MMCSD_CMD25,100))!=0) + if((ret=_MMCSD_WaitUntil(MMCSD_CMD_DONE,device->port))!=MMCSD_OK) + { + FAILED("WaitCMDDone ret 0x%lx",(unsigned long)ret); + goto dma_write_end; + } +#ifdef CONFIG_ARCH_MX2ADS + if(device->port == 1) + g_mmcsd_status = mmcsdr_status_2; + else + g_mmcsd_status = mmcsdr_status; +#endif +#ifdef CONFIG_ARCH_MX1ADS + g_mmcsd_status = mmcsdr_status; +#endif + if((g_mmcsd_status&0x40)==0) + { + FAILED("FIFO is not empty 0x%lx",(unsigned long)ret); + goto dma_write_end; + } + + /************************************************************** + * Enable DMA + **************************************************************/ + + // TRACE("Enable DMA.."); + // _MMCSD_StartClk(); + g_mmcsd_cmd[device->port] = 0xFF; +#ifdef CONFIG_ARCH_MX1ADS + enable_dma(device->dma_channel); +#endif +#ifdef CONFIG_ARCH_MX2ADS + mx_dma_start(device->dma_channel); +#endif + + timeleft = interruptible_sleep_on_timeout(&(device->select_wait),100); + if(!timeleft) + { + FAILED("write failed, Timeout!"); +#ifdef CONFIG_ARCH_MX1ADS + disable_dma(device->dma_channel); +#endif +#ifdef CONFIG_ARCH_MX2ADS + _reg_DMA_CCR(device->dma_channel) &= 0xFFFFFFFE; +#endif + g_mmcsd_cmd[device->port] = 0x0; + ret = MMCSD_ERROR; + goto dma_write_end; + } +#ifdef CONFIG_ARCH_MX1ADS + disable_dma(device->dma_channel); +#endif +#ifdef CONFIG_ARCH_MX2ADS + _reg_DMA_CCR(device->dma_channel) &= 0xFFFFFFFE; +#endif + g_mmcsd_cmd[device->port] = 0x0; + // TRACE("Waked up "); + + status = device->result; + // TRACE("waked up! status = %lx",status); + + counter = 0xFFFF; + while(counter--) + { +#ifdef CONFIG_ARCH_MX2ADS + if(device->port == 1) + g_mmcsd_status = mmcsdr_status_2; + else + g_mmcsd_status = mmcsdr_status; +#endif +#ifdef CONFIG_ARCH_MX1ADS + g_mmcsd_status = mmcsdr_status; +#endif + TRACE("g_mmcsd_status is 0x%0lX (for TRANS-DONE)",(unsigned long)g_mmcsd_status); + if((g_mmcsd_status&0x1007)==0) + { + mmcsd_delay(0xFFFF); + continue; + } + + if(g_mmcsd_status&0x0007) + { + ret = MMCSD_ERROR; + FAILED("status is 0x%lx",(unsigned long)g_mmcsd_status); + goto dma_write_end; + } + ret = MMCSD_OK; + break; + } + if(counter == 0) + { + ret = MMCSD_ERROR; + FAILED("TIME OUT.."); + goto dma_write_end; + } + + /******************************************************* + * Write Done + *******************************************************/ + if(ret==MMCSD_OK) + { + counter = 0xFFFF; + while(counter--) + { +#ifdef CONFIG_ARCH_MX2ADS + if(device->port == 1) + g_mmcsd_status = mmcsdr_status_2; + else + g_mmcsd_status = mmcsdr_status; +#endif +#ifdef CONFIG_ARCH_MX1ADS + g_mmcsd_status = mmcsdr_status; +#endif + TRACE("g_mmcsd_status is 0x%0lX (for Write-DONE)",(unsigned long)g_mmcsd_status); + if(g_mmcsd_status&0x0004) + { + TRACE("8)ERROR!"); + ret = MMCSD_ERROR; + break; + } + else if((g_mmcsd_status&0x1000)!=0) + { + ret = MMCSD_OK; + break; + } + mmcsd_delay(0xFFFF); + } + if(counter==0) + { + ret = MMCSD_ERROR; + FAILED("Time Out for Write-DONE."); + goto dma_write_end; + + } + } + +dma_write_end: + g_mmcsd_cmd[device->port] = 0; + + if((ret == MMCSD_OK)&&(device->cur_num>1)) + { + MMCSD_Responses rp; + // TRACE("CMD12 -- Last Block."); + ret2=_MMCSD_NoDataCommand(MMCSD_CMD12,0,MMCSDB_R1,device->port); + _MMCSD_GetResponses(&rp,MMCSDB_R1,device->port); + } + + // INFO("Check Status.....(after cmd12)"); + state =MMCSD_TRANSFER; + mmcsd_check_status(device,&state); + + if(int_mask != 0xFFFFFFFF) + { + // TRACE("Enable Interrupt."); + _MMCSD_Restore_Mask(int_mask,device->port); + } + + mmcsd_free_buffer(device); + // TRACE("15)return with ret = %lx,ret2 = %lx",ret,ret2); + return(ret|ret2); +} + +void mmcsd_free_buffer(MMCSD_Dev *device) +{ + + device->cur_num = 0; + device->addr = 0; +} + +/****************************************************************************** + * Function Name: mmcsd_sector_erase + * + * Input: + * device: the related device + * blks: the blocks that will be erased. + * + * Value Returned: + * 0: success. + * 1: failure. + * + * Description: + * this routine will erase indicated group. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +static int mmcsd_sector_erase(MMCSD_Dev *device, MMCSD_Blks *blks) +{ + int ret; + u32 state; + + TRACE("Erase the sector %ld ", (long int)(blks->start)); + + /******************************************************************** + * Lock the device. + *******************************************************************/ +#ifndef MMCSD_TEST + down_interruptible(&(device->sema)); + g_selected_lock[device->port].device = device; +#endif + + /******************************************************************** + * Identify the Card State ( Process only for Stand By State) + *******************************************************************/ + state =MMCSD_TRANSFER; + ret = mmcsd_check_status(device,&state); + if(ret) + { + FAILED(" Check Status failed."); + goto sector_erase_ret; + } + + /******************************************************************** + * Erase + *******************************************************************/ + + ret = _MMCSD_TagSectorStart(blks->start); + if(ret) + { + TRACE("TagSectorStart error"); + goto sector_erase_ret; + } + + //ret = _MMCSD_TagSectorEnd(blks->start); + ret = _MMCSD_TagSectorEnd(blks->start+device->phy_sectorsize-1); + if(ret) + { + TRACE("TagSectorEnd error"); + goto sector_erase_ret; + } + + ret = _MMCSD_Erase(); + if(ret) + { + TRACE("Erase error"); + goto sector_erase_ret; + } + +sector_erase_ret: + /******************************************************************** + * Unlock the selected device structure. + *******************************************************************/ + state =MMCSD_TRANSFER; + mmcsd_check_status(device,&state); +#ifndef MMCSD_TEST + up(&(device->sema)); +#endif + + + return ret; +} + +/****************************************************************************** + * Function Name: mmcsd_ReadBlock + * + * Input: None. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS mmcsd_ReadBlock(MMCSD_Dev *device,u32 start_addr,u16 nsects, u8 *buff ) +{ + u16 i; + u32 read_addr; + MMCSD_STATUS ret; + u8 *cur_buf; + /************************************************************************ + * Initialize local variables + *************************************************************************/ + ret = read_addr = 0; /* SEND/RECEIVE ERROR */ + + for ( i = 0 ; i < nsects ; i++ ) + { + /************************************************************ + * Set the first address of read sector + **************************************************************/ + read_addr = ( start_addr + (MMCSD_MINIMUM_BLK_SIZE*i) ); + /************************************************************ + * Create cmd + **************************************************************/ + cur_buf = buff+(MMCSD_MINIMUM_BLK_SIZE*i); + +#ifdef MMCSD_READ_DMA + + ret=mmcsd_DMA_ReadSingleBlock(device,read_addr, cur_buf); + if(ret==MMCSD_OK) // Only for DMA + { // Endian processing +#ifdef MMCSD_DMA_ENDIAN_ERR + _mmcsd_16_big_2_little(cur_buf,MMCSD_MINIMUM_BLK_SIZE); +#endif + } +#else + ret=mmcsd_ReadSingleBlock(device,read_addr, cur_buf); + +#endif + if (ret) + { + break; + } + } + return( ret ); +} + +/****************************************************************************** + * Function Name: mmcsd_ReadSingleBlock + * + * Input: None. + * + * Value Returned: + * + * MMCSD_STATUS + * + * Description: + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +MMCSD_STATUS mmcsd_DMA_ReadSingleBlock(MMCSD_Dev *device,u32 addr,u8 * buff) +{ + MMCSD_STATUS ret; + u32 channel,status,int_mask,state; + int timeleft; + + device->result = MMCSD_OK; + channel = device->dma_channel; + + ret = mmcsd_DmaStartTransfer( device, + buff, + MMCSD_MINIMUM_BLK_SIZE, + MMCSD_READ, + device->bit_width); + if(ret != MMCSD_OK) + { + FAILED("mmcsd_DmaStartTransfer failed !"); + return ret; + } + + state = MMCSD_TRANSFER; + ret = mmcsd_check_status(device,&state); + + _MMCSD_Mask_interrupt(0x7F,&int_mask,device->port); + + _MMCSD_StopClk(device->port); + + if(device->bit_width) + { + _MMCSD_SetCmd(MMCSD_CMD17,addr,MMCSD_BUS_4BIT|MMCSDB_DATEN|MMCSDB_R1,device->port); // Read Single BLK + } + else + { + _MMCSD_SetCmd(MMCSD_CMD17,addr,MMCSDB_DATEN|MMCSDB_R1,device->port); // Read Single BLK + } + g_mmcsd_cmd[device->port] = MMCSD_CMD17; + + _MMCSD_StartClk(device->port); + if((ret=_MMCSD_WaitUntil(MMCSD_CMD_DONE,device->port))!=0) + { + FAILED("WaitCMDDone ret 0x%lx",(unsigned long)ret); + goto dma_read_end; + } + TRACE("Enable DMA.."); +#ifdef CONFIG_ARCH_MX1ADS + enable_dma(channel); +#endif +#ifdef CONFIG_ARCH_MX2ADS + mx_dma_start(channel); +#endif + + timeleft = interruptible_sleep_on_timeout(&(device->select_wait),100); + if(!timeleft) + { + TRACE("read failed, Timeout!"); + ret = MMCSD_ERROR; + goto dma_read_end; + } + + status = device->result; + + TRACE("waked up! status = %x", status); + if(status&0x800) + { + ret = MMCSD_OK; + goto dma_read_end; + } + else if(status&0x3) + { + TRACE("g_mmcsd_status 0x%lx",(unsigned long)status); + ret = MMCSD_ERROR; + goto dma_read_end; + } + // in fact, although status&0x800 ==0, read succeed. + +dma_read_end: +#ifdef CONFIG_ARCH_MX1ADS + disable_dma(channel); +#endif +#ifdef CONFIG_ARCH_MX2ADS + //disable dma + _reg_DMA_CCR(channel) &= 0xFFFFFFFE; +#endif + _MMCSD_Restore_Mask(int_mask,device->port); + + g_mmcsd_cmd[device->port] = 0; + return ret; + +} + +MMCSD_STATUS mmcsd_ReadSingleBlock(MMCSD_Dev *device,u32 addr,u8 * buff) +{ + MMCSD_STATUS ret; + u32 temp32,j,int_mask,total; + u16 temp16; + u8 *pbuff; + int i; + + pbuff=buff; + + _MMCSD_Mask_interrupt(0x7F,&int_mask,device->port); + + total = 0; + _MMCSD_StopClk(device->port); //Ricky + + if(device->bit_width) + { + _MMCSD_SetCmd(MMCSD_CMD17,addr,MMCSD_BUS_4BIT|MMCSDB_DATEN|MMCSDB_R1,device->port); // Read Single BLK + } + else + { + _MMCSD_SetCmd(MMCSD_CMD17,addr,MMCSDB_DATEN|MMCSDB_R1,device->port); // Read Single BLK + } + g_mmcsd_cmd[device->port] = MMCSD_CMD17; + _MMCSD_StartClk(device->port); + + while(1) + { +#ifdef CONFIG_ARCH_MX2ADS + if(device->port == 1) + g_mmcsd_status = (mmcsdr_status_2); + else + g_mmcsd_status = (mmcsdr_status); +#endif +#ifdef CONFIG_ARCH_MX1ADS + g_mmcsd_status = (mmcsdr_status); +#endif + + if((g_mmcsd_status&0x088B) == 0) + { + continue; + } + + j = 0xFF; + while(j--); + + if(g_mmcsd_status&0x000B) + { + FAILED("Read Error (status = 0x%lx",(unsigned long)g_mmcsd_status); + ret = MMCSD_ERROR; + goto signle_read_end; + } + /* if(g_mmcsd_status&0x0008) + { + goto single_read_try_again; + } + */ + if((g_mmcsd_status&0x0080)!=0) // Buffer is FULL + { + //TRACE("FIFO is full"); + if(device->bit_width == 0) + { + for(i = 0;i < 8; i++) + { +#ifdef CONFIG_ARCH_MX2ADS + if(device->port == 1) + temp32 = mmcsdr_buffer_access_2; + else + temp32 = mmcsdr_buffer_access; +#endif +#ifdef CONFIG_ARCH_MX1ADS + // Aleph: certainly a Motorola pasto + //g_mmcsd_status = (mmcsdr_status); + temp32 = mmcsdr_buffer_access; +#endif + + temp16 = (u16)temp32; +#ifdef MMCSD_DMA_ENDIAN_ERR + *pbuff = (temp16&0xFF00)>>8; + pbuff++; + *pbuff = (temp16&0x00FF); + pbuff++; +#else + *pbuff = (temp16&0x00FF); + pbuff++; + *pbuff = (temp16&0xFF00)>>8; + pbuff++; +#endif + } + total += 16; + } + else + { + for(i = 0;i < 32; i++) + { +#ifdef CONFIG_ARCH_MX2ADS + if(device->port == 1) + temp32 = mmcsdr_buffer_access_2; + else + temp32 = mmcsdr_buffer_access; +#endif +#ifdef CONFIG_ARCH_MX1ADS + temp32 = mmcsdr_buffer_access; +#endif + + temp16 = (u16)temp32; +#ifdef MMCSD_DMA_ENDIAN_ERR + *pbuff = (temp16&0xFF00)>>8; + pbuff++; + *pbuff = (temp16&0x00FF); + pbuff++; +#else + *pbuff = (temp16&0x00FF); + pbuff++; + *pbuff = (temp16&0xFF00)>>8; + pbuff++; +#endif + } + total += 64; + } + } + + if((g_mmcsd_status&0x0800) != 0) // TRANS Done + { + //TRACE("Transfer done! g_mmcsd_status = 0x%x",g_mmcsd_status); + ret = MMCSD_OK; + goto signle_read_end; + + } + + // TRACE("Sleep on.. status=%x",g_mmcsd_status); + // interruptible_sleep_on(&(device->select_wait)); + // TRACE("Waked up ! status = 0x%x",g_mmcsd_status); + // + } + + +signle_read_end: + + _MMCSD_StopClk(device->port); + _MMCSD_Restore_Mask(int_mask,device->port); + + g_mmcsd_cmd[device->port] = 0; + return ret; + +} + +/****************************************************************************** + * Function Name: mmcsd_DmaStartTransfer + * + * Input: + * + * Value Returned: + * + * Description: + * + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +int mmcsd_DmaStartTransfer(MMCSD_Dev *device,u8 * buff,u32 counter, u8 mode,u8 is_4_bit) +{ + int channel; + + channel = device->dma_channel; + if(mode == MMCSD_READ) + { +#ifdef CONFIG_ARCH_MX1ADS + _reg_DMA_DAR(channel) = (u32)__virt_to_phys(buff); + _reg_DMA_SAR(channel) = (MMCSDR_BUFFER_ACCESS&0x0FFFFFFF); + _reg_DMA_CNTR(channel) = counter; + + _reg_DMA_CCR(channel) = 0x00000828; // Source Size = 16,Des Len = 32 + _reg_DMA_RSSR(channel) = 0xD; + if(is_4_bit) + { + _reg_DMA_BLR(channel) = 0x0; // Burst Len 64; + //_reg_DMA_BLR(channel) = 0x20; // Burst Len 32; + } + else + { + _reg_DMA_BLR(channel) = 0x10; // Burst Len 16; + } +#endif +#ifdef CONFIG_ARCH_MX2ADS + (device->dma).sourceType = DMA_TYPE_FIFO; + (device->dma).sourcePort = DMA_MEM_SIZE_16; + (device->dma).destType = DMA_TYPE_LINEAR; + (device->dma).destAddr = (u32)__virt_to_phys(buff); + (device->dma).destPort = DMA_MEM_SIZE_32; + (device->dma).count = counter; + if(device->port == 0) + { + (device->dma).sourceAddr = 0x10013038;//sdhc1, + (device->dma).request = 0x7;//sdhc1 + } + else + { + (device->dma).sourceAddr = 0x10014038;// for sdhc2 is 0x10014038 + (device->dma).request = 0x6;// sdhc2 is 0x6; + } + + if(is_4_bit) + { + (device->dma).burstLength = 0x0; //burst length 64 + } + else + { + (device->dma).burstLength = 0x10; //burst len 16 + } + mx_dma_set_config(device->dma_channel,&(device->dma)); + // mx_dump_dma_register(device->dma_channel); + +#endif + } + else + { +#ifdef CONFIG_ARCH_MX1ADS + // _reg_DMA_SAR(channel) = (u32)_MMCSD_get_phy_addr(buff); + _reg_DMA_SAR(channel) = (u32)__virt_to_phys(buff); + _reg_DMA_DAR(channel) = (MMCSDR_BUFFER_ACCESS&0x0FFFFFFF); + _reg_DMA_CNTR(channel) = counter; + + //_reg_DMA_CCR(channel) = 0x00002088; // Source Size = 32,Des Len = 16 + _reg_DMA_CCR(channel) = 0x2088; // Source Size = 32,Des Len = 16 + _reg_DMA_RSSR(channel) = 0xD; + + if(is_4_bit) + { + _reg_DMA_BLR(channel) = 0x0; // Burst Len 64; + //_reg_DMA_BLR(channel) = 0x20; // Burst Len 32; + } + else + { + _reg_DMA_BLR(channel) = 0x10; // Burst Len 16; + // _reg_DMA_BLR(channel) = 0x8; // Burst Len 8; + } +#endif +#ifdef CONFIG_ARCH_MX2ADS + (device->dma).sourceType = DMA_TYPE_LINEAR; + (device->dma).sourceAddr = (u32)__virt_to_phys(buff); + (device->dma).sourcePort = DMA_MEM_SIZE_32; + + (device->dma).destType = DMA_TYPE_FIFO; + (device->dma).destPort = DMA_MEM_SIZE_16; + + (device->dma).count = counter; + if(device->port == 0) + { + (device->dma).destAddr = 0x10013038;//sdhc1 + (device->dma).request = 7;//sdhc1 + } + else + { + (device->dma).destAddr = 0x10014038;//for sdhc2 is 0x10014038 + (device->dma).request = 0x6;//sdhc2 is 0x6; + } + + if(is_4_bit) + { + (device->dma).burstLength = 0x0; //burst length 64 + } + else + { + (device->dma).burstLength = 0x10; //burst len 16 + } + + mx_dma_set_config(device->dma_channel,&(device->dma)); + +#endif + } + + return MMCSD_OK; +} + +/****************************************************************************** + * Function Name: mmcsd_dma_handler + * + * Input: + * + * Value Returned: + * + * Description: + * + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +void mmcsd_dma_isr(void *arg) +{ + MMCSD_Dev *device; + + device = g_selected_lock[0].device; + + if(device == NULL) + { + TRACE("\nmmcsd_interrupt_handler: no device"); + return; + } + + g_mmcsd_status = (mmcsdr_status); + + + //TRACE("(status = 0x%x)",g_mmcsd_status); + + // if(g_mmcsd_status&0x803) // It should be here, but sometimes no 0x800 return. + { + device->result = g_mmcsd_status; + wake_up_interruptible(&(device->select_wait)); + // TRACE("Wake Up ..."); + } + +} + +#ifdef CONFIG_ARCH_MX2ADS +void mmcsd_dma_isr_1(void * arg) +{ + MMCSD_Dev *device; + + device = g_selected_lock[1].device; + + if(device == NULL) + { + TRACE("\nmmcsd_interrupt_handler: no device"); + return; + } + + g_mmcsd_status = (mmcsdr_status_2); + + + //TRACE("(status = 0x%x)",g_mmcsd_status); + + // if(g_mmcsd_status&0x803) // It should be here, but sometimes no 0x800 return. + { + device->result = g_mmcsd_status; + wake_up_interruptible(&(device->select_wait)); + // TRACE("Wake Up ..."); + } + +} +#endif + +void mmcsd_dma_err_isr(int error_type) +{ + MMCSD_Dev *device; + + device = g_selected_lock[0].device; + + if(device == NULL) + { + TRACE("mmcsd_interrupt_handler: no device"); + return; + } + + g_mmcsd_status = (mmcsdr_status); + + device->result = g_mmcsd_status; + TRACE("error_type = 0x%x",error_type); + + wake_up_interruptible(&(device->select_wait)); + +} + +#ifdef CONFIG_ARCH_MX2ADS +void mmcsd_irq_handler_2(int irq,void * data, struct pt_regs * pt) +{ + MMCSD_Dev *device; + + mmcsdr_int_mask_2 |= 0x40; + device = g_selected_lock[1].device; + if(device == NULL) + { + return; + } + g_mmcsd_status = (mmcsdr_status_2); + + device->result = g_mmcsd_status; + + if(g_mmcsd_cmd[device->port] != 0xFF) + { + wake_up_interruptible(&(device->select_wait)); + } +} +#endif + +void mmcsd_irq_handler(int irq,void * data, struct pt_regs * pt) +{ + MMCSD_Dev *device; + + mmcsdr_int_mask |= 0x40; + + device = g_selected_lock[0].device; + if(device == NULL) + { + return; + } + // TRACE("The Device not empty..."); + g_mmcsd_status = (mmcsdr_status); + //TRACE("irq is called (%d), g_mmcsd_status = 0x%0X",g_mmcsd_cmd,g_mmcsd_status); + + device->result = g_mmcsd_status; + + // TRACE("Wake up the deice.. (status 0x%x)",device->result); + + if(g_mmcsd_cmd[device->port] != 0xFF) + { + wake_up_interruptible(&(device->select_wait)); + } + +} +/****************************************************************************** + * Function Name: mmcsd_tasklet + * + * Input: + * + * Value Returned: + * + * Description: + * + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +/* + void mmcsd_tasklet() + { + MMCSD_Dev * device; + + device = g_selected_lock.device; + + if(device == NULL) + { + TRACE("\n mmcsd_tasklet: no device"); + return; + } + + switch (g_mmcsd_cmd) + { + + case MMCSD_CMD17: + + case MMCSD_CMD24: + + disable_dma(MMCSD_DMA_CHANNEL); + + device->result = get_dma_residue(MMCSD_DMA_CHANNEL); + + free_dma(MMCSD_DMA_CHANNEL); + + wake_up_interruptible(&(device->select_wait)); + + break; + default: + break; + + } + } + */ +/****************************************************************************** + * Function Name: mmcsd_ioctl + * + * Input: + * inode : the pointer to MS driver-related inode. + * filep : the pointer to MS driver-related file structure. + * command : the command number. + * argument: argument which depends on command. + * + * Value Returned: + * 0 : succeed + * 1 : fail + * + * Description: + * This routine will implement driver-specific functions. + * + * Modification History: + * 30 DEC,2001, Yiwei Zhao + *****************************************************************************/ + +static int mmcsd_ioctl(struct inode *inode, + struct file *filp, + unsigned command, + unsigned long argument) +{ + int num,ret; + MMCSD_Dev *device; + MMCSD_PWD *pwd; + MMCSD_Blks blks; + u32 addr; + + TRACE("mmcsd_ioctl is called!"); + num = MINOR(inode->i_rdev); + + if(!filp) + { + TRACE("called without filp"); + return -EIO; + } + + if(num > g_mmcsd_num) + { + return -ENODEV; + } + device = &g_mmcsd_devices[num]; + + switch(command) { + + case BLKFLSBUF: + case BLKRAGET: + return blk_ioctl(inode->i_rdev, command, argument); + + case BLKGETSIZE: + + if (!argument) return -EINVAL; /* NULL pointer: not valid */ + + if (copy_to_user((long *) argument, &(device->dev_size), sizeof (long))) + { + return -EFAULT; + } + return 0; + + case MMCSDSECTORSIZE: + + if (!argument) return -EINVAL; /* NULL pointer: not valid */ + + if(copy_to_user((u16 *)argument, + &(device->phy_sectorsize), + sizeof(u16))) + { + return -EFAULT; + } + return 0; + + case MMCSDERASESECTOR: + + if (!argument) return -EINVAL; /* NULL pointer: not valid */ + + if (copy_from_user(&blks, (MMCSD_Blks *)argument, sizeof (blks))) + { + return -EFAULT; + } + + return(mmcsd_sector_erase(device, &blks)); + + case MMCSDPROTECT: + + if (!argument) return -EINVAL; /* NULL pointer: not valid */ + if (copy_from_user(&addr,(u32*)argument, sizeof(u32))) + { + return -EFAULT; + } + return(mmcsd_write_protect(device,addr,1)); + + case MMCSDCLEPROTECT: + if (!argument) return -EINVAL; /* NULL pointer: not valid */ + if (copy_from_user(&addr,(u32*)argument, sizeof(u32))) + { + return -EFAULT; + } + + return(mmcsd_write_protect(device,addr,0)); + + case MMCSDSETPW: + case MMCSDRESETPW: + case MMCSDLOCK: + case MMCSDUNLOCK: + case MMCSDFORCERASE: + + pwd = (MMCSD_PWD *)kmalloc((2+((MMCSD_PWD *)argument)->len),GFP_KERNEL|GFP_DMA); + if(pwd == NULL) + { + TRACE("\nmmcsd_ioctl: kmalloc error"); + return 1; + } + + if (copy_from_user(pwd,(MMCSD_PWD *)argument, sizeof((2+((MMCSD_PWD *) argument)->len)))) + { + return -EFAULT; + } + ret = mmcsd_passwd_cmd(device,pwd); + + kfree(pwd); + + return(ret); + + default: + + return blk_ioctl(inode->i_rdev, command, argument); + + } + + return 0; /* unknown command */ +} + +/****************************************************************************** + * Function Name: mmcsd_write_protect + * + * Input: + * device: pointer to the specified device. + * addr: the address of the indicated group. + * is_set: TRUE, if set the write protection; False, clear + * the write protection. + * + * Value Returned: + * 0 : succeed + * 1 : fail + * + * Description: + * This routine will set/clear the write protection bit for addressed + * group. + * + * Modification History: + * 30 DEC,2001, Yiwei Zhao + *****************************************************************************/ + +static int mmcsd_write_protect(MMCSD_Dev *device,u32 addr, char is_set) +{ + int ret = 0; + +#ifndef MMCSD_TEST + down_interruptible(&(device->sema)); + g_selected_lock[device->port].device = device; +#endif + if(mmcsd_is_writeprotection(device)) + { + if(is_set) + { + ret = _MMCSD_SetWriteProt(addr); + if(ret) + { + TRACE("_MMCSD_SetWriteProt error"); + goto write_protect_ret; + } + } + else + { + ret = _MMCSD_ClearWriteProt(addr); + if(ret) + { + TRACE("_MMCSD_ClearWriteProt error"); + goto write_protect_ret; + } + } + } + else + { + INFO(" The card doesn't support the Write Protection Feature\n"); + ret = MMCSD_ERROR; + goto write_protect_ret; + } + +write_protect_ret: +#ifndef MMCSD_TEST + up(&(device->sema)); +#endif + return ret; +} + + +/****************************************************************************** + * Function Name: mmcsd_passwd_cmd + * + * Input: + * device: the device write to + * pwd: pointer to MMCSD_PWD structure. + * + * Value Returned: + * 0: success. + * 1: failure. + * + * Description: + * this routine will process passwd-related commands. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ + +static int mmcsd_passwd_cmd( MMCSD_Dev *device, + MMCSD_PWD *pwd) +{ + int ret,i; + u32 state,int_mask,temp32; + u16 temp16,*p16; + int burst_len,counter; + int total_len; // it's different from pwd->len. the latter is the actural pwd len. + // total_len is the total size that will be write to FIFO. + + + if((device->ccc&MMCSD_CCC_LOCK) ==0) + { + FAILED("The card doesn't support the feature."); + return MMCSD_ERROR; + } + + + total_len = (pwd->len+2) + (pwd->len%2); + //******************************************************************** + // Get Lock!!!!!!!!!!!!! + //******************************************************************** + +#ifndef MMCSD_TEST + down_interruptible(&(device->sema)); + g_selected_lock[device->port].device = device; +#endif + //******************************************************************** + // Check Status + //******************************************************************** + state =MMCSD_TRANSFER; + ret = mmcsd_check_status(device,&state); + if(ret) + { + TRACE("check status failed."); + ret = MMCSD_ERROR; + goto passwd_failed; + } + /************************************************************** + * Mask Interrupt + **************************************************************/ + TRACE("Disable Interrupt.."); + _MMCSD_Mask_interrupt(0x7F,&int_mask,0); + + /******************************************************************** + * Get the Lock for seclected device + *******************************************************************/ + + +#ifdef MMCSD_DMA_ENDIAN_ERR + _mmcsd_16_big_2_little((u8*)pwd, total_len); +#endif + /******************************************************************** + * Define the block length + *******************************************************************/ + + ret = _MMCSD_SetBlockLen(2+pwd->len,1,device->port); + if(ret) + { + FAILED("SetBlockLen error"); + ret = MMCSD_ERROR; + goto passwd_failed; + } + + if(device->bit_width == 1) + { + ret = _MMCSD_SetBusWidth(device->card_rca,2,device->port); + if(ret) + { + FAILED("Set Bus Width failed."); + ret = MMCSD_ERROR; + goto passwd_failed; + } + } + else + { + ret = _MMCSD_SetBusWidth(device->card_rca,0,device->port); + if(ret) + { + FAILED("Set Bus Width failed."); + ret = MMCSD_ERROR; + goto passwd_failed; + } + } + // while(_MMCSD_IsRun()) + _MMCSD_StopClk(0); //Ricky + + /******************************************************************** + * Process Passwd command + *******************************************************************/ + counter = 0; + p16 = (u16 *)pwd; + + TRACE("Begin Set Command.."); + if(device->bit_width == 0) + { + _MMCSD_SetCmd(MMCSD_CMD42,0,MMCSDB_DATEN|MMCSDB_R1|MMCSDB_WRRD,0); + burst_len = 8; + } + else + { + _MMCSD_SetCmd(MMCSD_CMD42,0,MMCSD_BUS_4BIT|MMCSDB_DATEN|MMCSDB_R1|MMCSDB_WRRD,0); + burst_len = 32; + } + g_mmcsd_cmd[device->port] = MMCSD_CMD42; + _MMCSD_StartClk(0); + /* if((ret=_MMCSD_WaitUntil(MMCSD_CMD_DONE))!=0) + { + FAILED("WaitCMDDone ret 0x%lx",ret); + goto passwd_failed; + } + */ + ret = MMCSD_OK; + while(ret == MMCSD_OK) + { + TRACE("g_mmcsd_status is 0x%0X",g_mmcsd_status); + g_mmcsd_status = (mmcsdr_status); + if((g_mmcsd_status&0x1047)==0) + { + TRACE("g_mmcsd_status is 0x%0X",g_mmcsd_status); + continue; + } + + // TRACE("g_mmcsd_status = 0x%x",g_mmcsd_status); + + if(g_mmcsd_status&0x0007) + { + TRACE("7)ERROR!--, g_mmcsd_status = %lx,counter = %d",(unsigned long)g_mmcsd_status,counter); + ret = MMCSD_ERROR; + goto passwd_failed; + } + else if((g_mmcsd_status&0x0040)!=0) // Buffer is empty + { + // TRACE("FIFO is empty!"); + for(i = 0;(i= total_len) + { + break; + } + } + + /******************************************************* + * Write Done + *******************************************************/ + if(ret==MMCSD_OK) + { + counter = 0xFFFF; + while(counter--) + { + g_mmcsd_status = mmcsdr_status; + if(g_mmcsd_status&0x0007) + { + FAILED("8)ERROR! status = 0x%lx",(unsigned long)g_mmcsd_status); + ret = MMCSD_ERROR; + break; + } + else if((g_mmcsd_status&0x1000)!=0) + { + TRACE("9)Write Done! g_mmcsd_status = 0x%lx",(unsigned long)g_mmcsd_status); + ret = MMCSD_OK; + break; + } + TRACE("10)g_mmcsd_status = %lx",(unsigned long)g_mmcsd_status); + } + } + +passwd_failed: + // _MMCSD_StopClk(); //Ricky + + TRACE("Enable Intr..."); + _MMCSD_Restore_Mask(int_mask,0); + state =MMCSD_TRANSFER; + mmcsd_check_status(device,&state); +#ifndef MMCSD_TEST + up(&(device->sema)); +#endif + + return ret; +} + +/****************************************************************************** + * Function Name: mmcsd_is_writeprotection + * + * Input: + * device: the device write to + * + * Value Returned: + * 1: the device support protection mechanism. + * + * Description: + * this routine test whether the device support protection mechanism. + * + * Modification History: + * 30 DEC,2001, Initial version. Yiwei Zhao + *****************************************************************************/ +static int mmcsd_is_writeprotection(MMCSD_Dev *device) +{ + if((device->ccc&MMCSD_CCC_WRPT)!=0) + { + return 1; + } + else + { + return 0; + } +} + + +static int mmcsd_getMBR(MMCSD_Dev * device) +{ + int ret=MMCSD_OK,i; + u8 * buf = NULL; + + buf = kmalloc(MMCSD_FS_SECTOR_SIZE*sizeof(u8), GFP_KERNEL|GFP_DMA); + if(!buf) + { + FAILED("kmalloc failed"); + return MMCSD_ERROR; + } + + for(i = 0; i < 512; i++) + { + *(buf+i)=0xAA; + } + ret = mmcsd_read(device, + buf, + 0, + 1); + if(ret) + { + FAILED("mmcsd_read() error!"); + ret = MMCSD_ERROR; + goto getMBR_error; + } + + + device->lba_sec_offset = (*(buf+0x1C6)) | + (*(buf+0x1C7))<<8 | + (*(buf+0x1C8))<<16| + (*(buf+0x1C9))<<24; + TRACE("lba_sec_offet is 0x%lx\n",device->lba_sec_offset); + TRACE("sect_num is 0x%lx\n",device->sect_num); + + if(device->lba_sec_offset > device->sect_num) + { + // PLAM -- if MBR is indeed a PBR, the sector offset to this partition is zero! + if(*buf==0xeb && *(buf+1)==0x3c && *(buf+2)==0x90) // starting bytes of a PBR + { + TRACE("PBR in place of MBR, lba_sec_offset is now set to 0\n"); + device->lba_sec_offset = 0; + } + else + { + // end PLAM + INFO("LBA is Wrong (%ld)",(long int)(device->lba_sec_offset)); + ret = MMCSD_ERROR; + // PLAM + } + // end PLAM + } + +getMBR_error: + + kfree(buf); + return ret; + +} +void _mmcsd_16_big_2_little(u8 *buf, u32 size) +{ + u8 *p; + u16 temp16; + u32 j; + + p = buf; + + for(j = 0; j< size/2; j++) + { + temp16 = (*(u16 *)p); + + + *(u8 *)p = (temp16&0xFF00)>>8; + (u8 *)p++; + *(u8 *)p = (temp16&0x00FF); + (u8*)p++; + } +} +void _mmcsd_cp_16_little_2_big(u8 *src,u8 *target, int size) +{ + int i; + u16 tmp16,*p16; + + p16 = (u16 *)target; + for(i = 0;i < size/2; i++) + { + tmp16 = (*src<<8); + src++; + tmp16 = tmp16|(*src); + src++; + *p16 = tmp16; + p16++; + + } +} +void _mmcsd_print_page(u8 *cur_buf, u32 size) +{ + int j; + + for(j = 0; j < size; j++) + { + if(j%16 == 0) printk("\n 0x%04X\t ---",j); + printk(" %02x ", (u8)(*(cur_buf+j))); + } + printk("\n"); +} + +u8 * test_buf[MMCSD_TEST_PAGE_NUM]; +void _mmcsd_test_reading_pages(MMCSD_Dev * device) +{ + u8 i; + u32 ret; + + for( i = 0;i < MMCSD_TEST_PAGE_NUM; i++) + { + test_buf[i] = kmalloc(MMCSD_FS_SECTOR_SIZE*sizeof(u8), GFP_KERNEL|GFP_DMA); + } + // buf2=buf3=buf4=buf1; + + + for( i = 0;i < MMCSD_TEST_PAGE_NUM; i++) + { + memset(test_buf[i],0xAA,MMCSD_FS_SECTOR_SIZE); + ret = mmcsd_read(device, + test_buf[i], + TESTING_PAGE+i, + 1); + TRACE("Sector %d",TESTING_PAGE+i); + _mmcsd_print_page(test_buf[i],512); + } + + for( i = 0;i < MMCSD_TEST_PAGE_NUM; i++) + { + kfree(test_buf[i]); + } +} + +void mmcsd_delay(u32 delay) +{ + while(delay--); +} + +static int handle_pm_event(struct pm_dev *dev, pm_request_t rqst, void *data) +{ + MMCSD_Dev *device1; +#ifdef CONFIG_ARCH_MX2ADS + MMCSD_Dev *device2; + + device2 = &g_mmcsd_devices[1]; +#endif + device1 = &g_mmcsd_devices[0]; + + switch(rqst) + { + case PM_SUSPEND: + INFO("MMC will comes into Suspend state"); + spin_lock(&device1->lock); + down_interruptible(&(device1->sema)); +#ifdef CONFIG_ARCH_MX2ADS + spin_lock(&device2->lock); + down_interruptible(&(device2->sema)); + //pin pe18~23,18,19,20,22 up, 21-dat3,23-clk + _reg_GPIO_DDIR(GPIOE) &= ~0x00fc0000; + _reg_GPIO_GIUS(GPIOE) |= 0xff03ffff; + _reg_GPIO_PUEN(GPIOE) |= 0x00fc0000; + + //add for SD2 pb4~pb9 pb7-dat3,pb9-clk + _reg_GPIO_DDIR(GPIOB) &= ~0x000003f0; + _reg_GPIO_GIUS(GPIOB) |= 0x000003f0; + _reg_GPIO_PUEN(GPIOB) |= 0x000003f0; + _MMCSD_StopClk(0); + _MMCSD_StopClk(1); + + +#endif + //pb8~13, 11-dat3,12-clk,13-cmd +#ifdef CONFIG_ARCH_MX1ADS + /* + *(u32 *)DBMX1_DDIR_B &= ~0x00003F00; // Enable SDHC's port to Output + *(u32 *)DBMX1_GIUS_B |= 0x00003F00; + *(u32 *)DBMX1_PUEN_B |= 0x00003F00; + */ + _MMCSD_StopClk(0); +#endif + break; + case PM_RESUME: + INFO("MMC will be resumed."); + + up(&(device1->sema)); + spin_unlock(&device1->lock); +#ifdef CONFIG_ARCH_MX2ADS + up(&(device2->sema)); + spin_unlock(&device2->lock); + if(device2->card_type != MMCSD_NO_CARD) + { + + _MMCSD_InitSDHC(1); + _MMCSD_64M_MMC_PinConfig(); + } +#endif + if(device1->card_type != MMCSD_NO_CARD) + { + _MMCSD_InitSDHC(0); + _MMCSD_64M_MMC_PinConfig(); + } + _MMCSD_SetClk(MMCSD_HIGH_SPEED,0); +#ifdef CONFIG_ARCH_MX2ADS + _MMCSD_SetClk(MMCSD_HIGH_SPEED,1); +#endif + + break; + default: + break; + } + return 0; +} + +#ifndef MODULE +module_init(mmcsd_init); +module_exit(mmcsd_cleanup); +#endif diff -Nru src.org/drivers/mx1mmc/mmc_main.h src/drivers/mx1mmc/mmc_main.h --- src.org/drivers/mx1mmc/mmc_main.h Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/mmc_main.h Wed Oct 12 23:09:11 2005 @@ -0,0 +1,501 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2002 Motorola Semiconductors HK Ltd + * + */ + +/****************************************************************************** + * + * Copyright (C) 2001, Motorola All Rights Reserved + * + * File Name: mmcsd_main.h + * + * Progammers: Yiwei Zhao + * + * Date of Creations: 30 Nov 2001 + * + * Synopsis: + * + * Modification History: + * 30 Nov, 2001, initialization version + * + *****************************************************************************/ + +/* + * Implementation of the MultiMediaCard/SD Driver. + */ +#ifndef _MOT_MMC_SD_MAIN_H_ +#define _MOT_MMC_SD_MAIN_H_ +#include +#include +#include +#include + +#ifdef CONFIG_ARCH_MX2ADS +#include +#include +#endif +#include "sys_mmc.h" + + +#ifdef SILICON_MASK_0L +// only needed if 0L44N/0L45N is used. Add -DMASK_SILICON_0L to Makefile if using 0L44N/0L45N +#define MMCSD_DMA_ENDIAN_ERR 1 +#endif + +#define MMCSD_TEST 1 +#define MMCSD_WRITE_DMA 1 +#define MMCSD_READ_DMA 1 +//#define MMCSD_CMD 1 + +//#define DBMX1_DEBUG 1 +#ifdef DBMX1_DEBUG +#define TRACE(fmt, args...) \ + { \ + printk("\n %s:%d:%s:",__FILE__, __LINE__,__FUNCTION__); \ + printk(fmt, ## args);\ + } +#else +#define TRACE(fmt, args...) +#endif + +#define FAILED(fmt, args...) \ + { \ + printk("\n %s:%d:%s:",__FILE__, __LINE__,__FUNCTION__); \ + printk(fmt, ## args);\ + } + +#define INFO(fmt, args...) \ + { \ + printk("\n"); \ + printk(fmt, ## args);\ + } + + +/***************************************************************************** + * + * Macro Definition + * + ****************************************************************************/ + +/* 3.2. Constant Definition + * 3.2.1.Addresses of Registers + * The following macros define the addresses of SDHC's registers. + */ + +/* 3.2.2 Card State + *The macros define the states of MMC/SD card. + */ +#define MMCSD_NOTREADY 0x0 /*Initial State*/ +#define MMCSD_INACTIVE 0x1 /*Inactive State*/ + + +#define MMCSD_IDLE 0x0 /*Idle State*/ +#define MMCSD_READY 0x200 /*Ready State */ +#define MMCSD_IDENTIFICATION 0x400 /*Identification State */ +#define MMCSD_STANDBY 0x600 /*Stand-by State*/ +#define MMCSD_TRANSFER 0x800 /*Transfer State*/ +#define MMCSD_SEND_DATA 0xA00 /*Sending State*/ +#define MMCSD_RECEIVE_DATA 0xC00 /*Receiving State*/ +#define MMCSD_PROGRAM 0xE00 /*Programming State*/ +#define MMCSD_DISCONNECT 0x1000 /* Disconnect State*/ +#define MMCSD_STATUS_STATE 0x00001E00 + +/* 3.2.3. Read Ahead Value + * This macro defines the block-level read-ahead values for MMCSD driver. + */ +#define MMCSD_READ_AHEAD 8 + +/* 3.2.4. Device Number + * This macro defines the number of devices that MS driver will manage. + */ +#define MMCSD_DEVICE_NUM 2 + +/* 3.2.5. Block and Sector Size + * These macros define the sector size and minimum block size, which are + * required by Linux Block Driver. + */ +#define MMCSD_MINIMUM_BLK_SIZE 512 +#define MMCSD_FS_SECTOR_SIZE MMCSD_MINIMUM_BLK_SIZE +#define MMCSD_MINIMUM_BLK_SIZE_BIT 9 +#define MMCSD_MAX_MULTI_BLK 64 + +/* MMCSD Major Numner + * + */ + +#define MMCSD_MAJOR 0x78 + +/* MMCSD Interrupr Number + * + */ +#ifdef CONFIG_ARCH_MX2ADS +#define MMCSD_IRQ 11 +#define MMCSD2_IRQ 10 +#define MMCSD_SOCKET1_INT 8 //PD25 +#endif +#ifdef CONFIG_ARCH_MX1ADS +#define MMCSD_IRQ 35 +#define MMCSD_SOCKET1_INT 12 //PB20 +#endif +/* MMCSD DMA Channel + * + */ +#ifdef CONFIG_ARCH_MX2ADS +#define MMCSD_DMA_CHANNEL 0x7 +#endif +#ifdef CONFIG_ARCH_MX1ADS +#define MMCSD_DMA_CHANNEL 0xD +#endif +#define MMCSD_READ 0x1 +#define MMCSD_WRITE 0x2 + +/* + * For Setting Start Stop Speed + */ +#define MMCSD_HIGH_SPEED 0 // 20M 16M +#define MMCSD_LOW_SPEED 1 // As Low as possible + + + + + +/***************************************************************************** + * + * Structure Definition + * + ****************************************************************************/ + +/* 3.3. Structure Definition + * 3.3.1. Card Status + * Structure of MMCSD Card Status Register + */ +/* typedef struct _CARD_STATUS { + + UINT32 res1 :5; + UINT32 app_cmd :1; + UINT32 res2 :2; + UINT32 ready_for_data :1; + UINT32 cur_state :4; + UINT32 erase_reset :1; + UINT32 card_ecc_disabled :1; + UINT32 wp_erase_skip :1; + UINT32 cidcsd_overwrite :1; + UINT32 overrun :1; + UINT32 underrun :1; + UINT32 error :1; + UINT32 cc_error :1; + UINT32 card_ecc_failed :1; + UINT32 illegal_cmd :1; + UINT32 com_crc_error :1; + UINT32 lock_unlock_failed :1; + UINT32 card_is_locked :1; + UINT32 wp_violation :1; + UINT32 erase_param :1; + UINT32 erase_seq_error :1; + UINT32 block_len_error :1; + UINT32 address_error :1; + UINT32 out_of_range :1; + + } MMCSD_CARD_STATUS; +*/ + +/* 3.3.2. SDHC Status Register + * Structure of SDHC Status Register + */ +/* + typedef struct _SDHC_STAT { + + UINT32 timeout_read :1; + UINT32 timeout_reponse :1; + UINT32 crc_werror :1; + UINT32 crc_rerror :1; + UINT32 res1 :1; + UINT32 crc_resperror :1; + UINT32 app_bfe :1; + UINT32 app_bff :1; + UINT32 clock_running :1; + UINT32 wr_crc_error :2; + UINT32 data_tran_done :1; + UINT32 access_op_done :1; + UINT32 end_cmd_resp :1; + UINT32 irq_active :1; + UINT32 card_presence :1; + UINT32 res2 :16; + + } DBMX1_SDHC_STATUS; +*/ +/* 3.3.3 SDHC Clock Rate Register + */ + + typedef struct _SDHC_CLK_RATE { + + u32 clk_rate :3; + u32 pre_scaler :3; + u32 res1 :26; + + } DBMX1_SDHC_CLK_RATE; + +/* 3.3.4 Command and Data Control Register + */ + + typedef struct _SDHC_CMD_DAT_CONT { + + u32 resp_format :3; + u32 data_enable :1; + u32 write_read :1; + u32 stream_block :1; + u32 busy :1; + u32 initialize :1; + u32 bus_width :2; + u32 start_read_wait :1; + u32 stop_read_wait :1; + u32 cmdres :1; + u32 res :19; + + } DBMX1_SDHC_CMD_DAT_CONT; + +/* 3.3.5 Interrupt Mask Register + */ +/* + typedef struct _SDHC_INT_MASK { + + UINT32 data_tran :1; + UINT32 prg_done :1; + UINT32 end_cmd_res :1; + UINT32 buf_ready :1; + UINT32 sdio_interrupt :1; + UINT32 dat0_irq :1; + UINT32 auto_card :1; + UINT32 res :25; + + } DBMX1_SDHC_INT_MASK; +*/ +/* 3.3.6 MMCSD Device Structure + * + */ + typedef struct _MMCSD_Dev { + + u8 CID[16]; + u32 card_rca; // card address + u32 card_state; // current state of the card + + u32 dev_size; + u32 sect_num; + u8 blksize_bit; + u32 blksize; // size of block in file system + + u16 phy_blksize; // Physical size of block on the MMCSD. + u32 phy_sectorsize; // the size of erasable sector + u32 wp_grp_size; // the size of write protected group + + spinlock_t lock; + struct semaphore sema; + u32 usage; + +// request_queue_t queue; // request queue + u8 busy; + int kpid; + + wait_queue_head_t select_wait; // Kernel thread blocked on it. +// wait_queue_head_t dma_wait; // Kernel thread blocked on it. + u8 cmd; // What command being executed. + u32 result; // set by tasklet + u8 *buff; + + u8 card_type; + u8 bit_width; //1: 4-bit, 0: 1-bit + u32 lba_sec_offset; + + u8 *buff_pool[MMCSD_MAX_MULTI_BLK]; +#ifdef MMCSD_DMA_ENDIAN_ERR + u8 *tmp_pool[MMCSD_MAX_MULTI_BLK]; +#endif + u32 cur_num; + u32 cur_sec; + u32 addr; + + u32 dma_channel; +#ifdef CONFIG_ARCH_MX2ADS + dma_request_t dma; +#endif + u32 is_ro; + u32 port;//in MX21 there are two ports + u16 ccc; // Card Command Class + + } MMCSD_Dev; + +/* The Lock for Current Selected Device + * + */ + +typedef struct _selected_lock{ + + spinlock_t lock; + MMCSD_Dev *device; +}MMCSD_Lock; + +/* 3.3.7 MMCSD Blocks + * + */ + typedef struct _MMCSD_Blks { + + u32 start; // start address + + }MMCSD_Blks; + +/* 3.3.8 MMCSD Password Structure + * + */ + typedef struct _MMCSD_PWD { + + u8 set_pwd :1; // new password + u8 clr_pwd :1; // clear password + u8 lock :1; // lock, 0 unlock + u8 erase :1; // Forced Erase + u8 res :4; + u8 len; // length of password + u8 pwd[256]; + + }MMCSD_PWD; + + +typedef union _Responses { + + u32 status; + u32 OCR; + u8 CID[16]; + u8 CSD[16]; + u8 SCR[8]; +}MMCSD_Responses; + +typedef struct tag_csd{ + + u8 csd_structure; /* CSD structure */ + u8 mmc_prot; /* MMC protocol version */ + u16 read_bl_len; /* read data block length */ + u32 c_size; /* device size */ + u16 sector_size; /* erase sector size */ +}MMC_CSD; + +/***************************************************************************** + * + * Extern Variables + * + ****************************************************************************/ + +extern MMCSD_Dev *g_mmcsd_devices; +extern u8 g_mmcsd_cur_device; +extern u8 g_mmcsd_num; +extern MMCSD_Lock g_selected_lock[2]; + +/***************************************************************************** + * + * Function Declarations + * + ****************************************************************************/ +/* Functions in mmcsd_drv.c*/ + +MMCSD_STATUS _MMCSD_InitCard(void); +MMCSD_STATUS _MMCSD_InitMMC(int port); +MMCSD_STATUS _MMCSD_GetInfo(MMCSD_Dev *device); +MMCSD_STATUS _MMCSD_SetSectLen(MMCSD_Dev *device); +u32 _MMCSD_GetStatus(MMCSD_Dev *device); +void _MMCSD_SetCSD(MMCSD_Dev *device,u8 * Csd_buff); +MMCSD_STATUS _MMCSD_CSDCheck(u8 *csdbuff ); +MMCSD_STATUS _MMCSD_CIDCheck( u8 *cidbuff ); +void _MMCSD_SetCID(MMCSD_Dev *device,u8* Cid_buff); +MMCSD_STATUS _MMCSD_InitSDHC(int port); +//MMCSD_STATUS _MMCSD_SCRCheck(MMCSD_Dev *device); + +/* Functions in mmcsd_cmd.c*/ + +MMCSD_STATUS _MMCSD_GoIdleState(int port); +MMCSD_STATUS _MMCSD_SendOpCond(u32 voltage,int port); + +MMCSD_STATUS _MMCSD_AllSendCID(u8 *pCidBuff,int port); +MMCSD_STATUS _MMCSD_SetRelativeAddr(u32 *addr,int port); +MMCSD_STATUS _MMCSD_SelectDeselectCard(u32 addr,u32 port); +MMCSD_STATUS _MMCSD_SendCSD(u32 addr,u8* pBuff,u32 port); +MMCSD_STATUS _MMCSD_SendCID(u32 addr,u8 * pBuff,u32 port); +MMCSD_STATUS _MMCSD_SendStatus(u32 addr,u32 *pStatus,u32 port); +MMCSD_STATUS _MMCSD_SetBlockLen(u32 size,u32 num,u32 port); +MMCSD_STATUS _MMCSD_TagSectorStart(u32 addr); +MMCSD_STATUS _MMCSD_TagSectorEnd(u32 addr); +MMCSD_STATUS _MMCSD_Erase(void); +MMCSD_STATUS _MMCSD_NoDataCommand(u8 cmd, u32 arg,u32 ctrl,int port); +MMCSD_STATUS _MMCSD_WaitUntil(u32 EndCondition,int port); +MMCSD_STATUS _MMCSD_SetBusWidth(u32 rca, u32 width,u32 port); +void _MMCSD_Mask_interrupt(u32 mask, u32 *orig,int port); +void _MMCSD_Restore_Mask(u32 orig,int port); +MMCSD_STATUS _MMCSD_irq_WaitUntil(u32 EndCondition,u8 cmd,int timeout,int port); +//MMCSD_STATUS _MMCSD_SendSCR(u32 rca,MMCSD_scr *scr, u32 port); + + +/* Functions in mmcsd_io.c */ + +u32 _MMCSD_ChectHardwareRevision(int port); +u32 _MMCSD_SoftReset(int port); +void _MMCSD_SetCmd(u8 cmd,u32 arg,u32 ctrl,int port); +u32 _MMCSD_IsRun(int port); +void _MMCSD_StartClk(int port); +void _MMCSD_StopClk(int port); +void _MMCSD_GetResponses(MMCSD_Responses *pRS, u8 rsType,int port); +void _MMCSD_SetBlockLenReg(u16 size,u32 port); +void _MMCSD_SetNumberOfBlockReg(u16 num,u32 port); +void Start_Stop_Clk(u32 Clk_en,int port); +void _MMCSD_ClockSet(u32 prescaler,u8 clk,int port); +void _MMCSD_ReadTimeOut(u32 arg,int port); +void _MMCSD_64M_MMC_PinConfig(void); +void _MMCSD_SetClk(int mode,int port); + +void _mmcsd_socket1_clear_irq(void); +void _mmcsd_socket1_irq_set(void); + +/* Functions in SysInit.c */ +/* +void Set_P2CLK(void); +void PortB_AIPI_IRQ_setting(void); +void SysInit(void); +void PWMInit(void); +void DSPAInit(void); +void MMCInit(void); +void LCDCInit(void); +void ASPInit(void); +void MemInit(void); +void PortInit(void); +void ClockInit(UINT8 clock); +void AIPIInit(void); +void IrptInit(void); +void LED3_off(void); +void LED3_on(void); +void LED2_off(void); +void LED2_on(void); +*/ +/* Functions for Testing */ + +void _mmcsd_test_reading_pages(MMCSD_Dev * device); +void _mmcsd_print_page(u8 * p, u32 size); + +#define MMCSD_OK 0 +#define MMCSD_ERROR -1 + +//#define _MMCSD_get_phy_addr(buf) (buf-0xc0000000+0x08000000) + + +#endif + + diff -Nru src.org/drivers/mx1mmc/sys_mmc.h src/drivers/mx1mmc/sys_mmc.h --- src.org/drivers/mx1mmc/sys_mmc.h Thu Jan 1 08:00:00 1970 +++ src/drivers/mx1mmc/sys_mmc.h Fri Sep 23 20:26:30 2005 @@ -0,0 +1,34 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2002 Motorola Semiconductors HK Ltd + * + */ + + +/* ioctl commands + * + */ + +#define MMCSD_IOCTL_MAGIC ('X') +#define MMCSDERASESECTOR _IOR(MMCSD_IOCTL_MAGIC, 0, unsigned int) +#define MMCSDPROTECT _IOW(MMCSD_IOCTL_MAGIC, 1, unsigned int) +#define MMCSDCLEPROTECT _IOW(MMCSD_IOCTL_MAGIC, 2, unsigned int) +#define MMCSDSETPW _IOW(MMCSD_IOCTL_MAGIC, 3, unsigned int) +#define MMCSDRESETPW _IOW(MMCSD_IOCTL_MAGIC, 4, unsigned int) +#define MMCSDLOCK _IOW(MMCSD_IOCTL_MAGIC, 5, unsigned int) +#define MMCSDUNLOCK _IOW(MMCSD_IOCTL_MAGIC, 6, unsigned int) +#define MMCSDFORCERASE _IOW(MMCSD_IOCTL_MAGIC, 7, unsigned int) +#define MMCSDSECTORSIZE _IOW(MMCSD_IOCTL_MAGIC, 8, unsigned int) diff -Nru src.org/init/main.c src/init/main.c --- src.org/init/main.c Tue Jul 22 15:54:12 2003 +++ src/init/main.c Wed Oct 5 16:41:51 2005 @@ -148,6 +148,7 @@ const int num; } root_dev_names[] __initdata = { // MX1ADS - mdsk is added to the top, otherwise kernel may confuse it with "md" + { "mmc", 0x7800 }, { "docbp", 0x6300 }, { "mdsk", 0x8000 }, { "sdisk2m", 0x8201 }, @@ -826,7 +827,7 @@ (void) dup(0); (void) dup(0); - + /* * We try each of these until one succeeds. *