Anish Mangal

Design Engineer at Freescale Semiconductor; July 2008 - Sep 2010

Summary of completed tasks in chronological order

• System performance analysis

The objective of this activity was to ascertain whether a particular bus-arbiter was capable of handling the bandwidth requirements inside the P1022 Multicore System-on-Chip (SoC). It involved studying the system bus architecture and the bus arbitration scheme in detail and simulating various load and traffic conditions to determine the required performance metrics. The results from this activity helped the P1022 Architecture team take an informed decision.

• Verification of SoC specific IP Block, Common On-chip Processor (COP)

It involved the complete verification cycle of the COP block including RTL and Gate Level verification. The COP block in P1022 contained the Power Management, Reset, Clocking and Debug sub-blocks. Developed new testbench components (such as monitors) as a part of this activity.

• Developed a methodology for low power verification of designs containing multiple power domains

The P1022 multicore SoC features advanced low power modes such as Deep-Sleep, wherein a portion of the design is powered OFF. Verifying this feature required the development of a flow to automatically generate checkers by obtaining information from the design. This work was later published as a defensive publication.

• Silicon bringup and validation

Worked with the P1022 silicon validation team in the debug and bringup of the SoC. It involved many hands-on debug sessions on various boards developed specifically for the P1022 SoC. I also assisted the PLL characterization team in their analysis of various PLL's (System, Core, DDR) in the design.

• P1022 Rev 1.1 activities

P1022 implemented an advanced ultra deep-sleep mode resulting in drastic power savings. I was involved with the conception, design and simulation of corner cases of this advanced deep-sleep mode. Got recognition from the organisation in the form of a financial reward. Apart from this, carried of the RTL and gate level verification of many IP blocks in the design.

(Tentative) Technical Consultant at Paraguay Educa; Nov 2010 - Apr 2011

It will involve providing technical insight and support to the OLPC deployment in Paraguay.